Mem: Separate the host and guest views of memory backing store

This patch moves all the memory backing store operations from the
independent memory controllers to the global physical memory. The main
reason for this patch is to allow address striping in a future set of
patches, but at this point it already provides some useful
functionality in that it is now possible to change the number of
memory controllers and their address mapping in combination with
checkpointing. Thus, the host and guest view of the memory backing
store are now completely separate.

With this patch, the individual memory controllers are far simpler as
all responsibility for serializing/unserializing is moved to the
physical memory. Currently, the functionality is more or less moved
from AbstractMemory to PhysicalMemory without any major
changes. However, in a future patch the physical memory will also
resolve any ranges that are interleaved and properly assign the
backing store to the memory controllers, and keep the host memory as a
single contigous chunk per address range.

Functionality for future extensions which involve CPU virtualization
also enable the host to get pointers to the backing store.

3 files changed, 11 insertions, 3 deletions

diff --git a/src/sim/root.cc b/src/sim/root.cc
index 34150083d..b8fadf190 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -146,7 +146,7 @@ Root::unserialize(Checkpoint *cp, const std::string &section)
         warn("!!!! Checkpoint ver %#x is older than current ver %#x !!!!\n",
                 cpt_ver, gem5CheckpointVersion);
         warn("You might experience some issues when restoring and should run "
-             "the checkpoint upgrader (util/cpt_upgrade.py) on your "
+             "the checkpoint upgrader (util/cpt_upgrader.py) on your "
              "checkpoint\n");
         warn("**********************************************************\n");
     } else if (cpt_ver > gem5CheckpointVersion) {
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index fdb0f4033..c0c0b63ff 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -57,7 +57,7 @@ class SimObject;
  * SimObject shouldn't cause the version number to increase, only changes to
  * existing objects such as serializing/unserializing more state, changing sizes
  * of serialized arrays, etc. */
-static const uint64_t gem5CheckpointVersion = 0x0000000000000001;
+static const uint64_t gem5CheckpointVersion = 0x0000000000000002;
 
 template <class T>
 void paramOut(std::ostream &os, const std::string &name, const T &param);
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 65eb0e3eb..dae09b85a 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -58,6 +58,7 @@
 #include "debug/Loader.hh"
 #include "debug/WorkItems.hh"
 #include "kern/kernel_stats.hh"
+#include "mem/abstract_mem.hh"
 #include "mem/physical.hh"
 #include "params/System.hh"
 #include "sim/byteswap.hh"
@@ -81,7 +82,7 @@ System::System(Params *p)
       virtProxy(_systemPort),
       loadAddrMask(p->load_addr_mask),
       nextPID(0),
-      physmem(p->memories),
+      physmem(name() + ".physmem", p->memories),
       memoryMode(p->mem_mode),
       workItemsBegin(0),
       workItemsEnd(0),
@@ -342,6 +343,10 @@ System::serialize(ostream &os)
     SERIALIZE_SCALAR(pagePtr);
     SERIALIZE_SCALAR(nextPID);
     serializeSymtab(os);
+
+    // also serialize the memories in the system
+    nameOut(os, csprintf("%s.physmem", name()));
+    physmem.serialize(os);
 }
 
 
@@ -353,6 +358,9 @@ System::unserialize(Checkpoint *cp, const string &section)
     UNSERIALIZE_SCALAR(pagePtr);
     UNSERIALIZE_SCALAR(nextPID);
     unserializeSymtab(cp, section);
+
+    // also unserialize the memories in the system
+    physmem.unserialize(cp, csprintf("%s.physmem", name()));
 }
 
 void