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author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-09-22 10:07:11 +0100 |
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committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
commit | 992fa9958da913aa1a40c78dd566d6498ee7d610 (patch) | |
tree | 6c5447e40b33e21029089f869096b65678a91906 /src/sim | |
parent | 2f6d69ee08bd92d9fcfb9b78f84b2d7c0ba113d0 (diff) | |
download | gem5-992fa9958da913aa1a40c78dd566d6498ee7d610.tar.xz |
mem: Support for specifying the destination of a WriteClean
Previously, WriteClean packets would always write to the first memory
below unless the memory was unable to allocate in which case it would
be forwarded further below.
This change adds support for specifying the destination of a
WriteClean packet. The cache annotates the request with the specified
destination and marks the packet as write-through upon its
creation. The coherent xbar checks packets for their destination and
resets the write-through flag when necessary e.g., the coherent xbar
that is set as the PoC will reset the write-through flag for packets
to the PoC.
Change-Id: I84b653f5cb6e46e97e09508649a3725d72d94606
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5046
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/sim')
0 files changed, 0 insertions, 0 deletions