Merge vm1.(none):/home/stever/bk/newmem-head

into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : fba7efd444e1ca9738385dd4662a33feab357e79

4 files changed, 138 insertions, 0 deletions

diff --git a/src/sim/Process.py b/src/sim/Process.py
new file mode 100644
index 000000000..16be65fd4
--- /dev/null
+++ b/src/sim/Process.py
@@ -0,0 +1,51 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+class Process(SimObject):
+    type = 'Process'
+    abstract = True
+    output = Param.String('cout', 'filename for stdout/stderr')
+    system = Param.System(Parent.any, "system process will run on")
+
+class LiveProcess(Process):
+    type = 'LiveProcess'
+    executable = Param.String('', "executable (overrides cmd[0] if set)")
+    cmd = VectorParam.String("command line (executable plus arguments)")
+    env = VectorParam.String('', "environment settings")
+    cwd = Param.String('', "current working directory")
+    input = Param.String('cin', "filename for stdin")
+    uid = Param.Int(100, 'user id')
+    euid = Param.Int(100, 'effective user id')
+    gid = Param.Int(100, 'group id')
+    egid = Param.Int(100, 'effective group id')
+    pid = Param.Int(100, 'process id')
+    ppid = Param.Int(99, 'parent process id')
diff --git a/src/sim/Root.py b/src/sim/Root.py
new file mode 100644
index 000000000..fff998e0d
--- /dev/null
+++ b/src/sim/Root.py
@@ -0,0 +1,34 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class Root(SimObject):
+    type = 'Root'
+    dummy = Param.Int(0, "We don't support objects without params")
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 46dc2c8dd..50f966bcf 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+SimObject('Root.py')
+SimObject('System.py')
+
 Source('async.cc')
 Source('builder.cc')
 Source('core.cc')
@@ -50,5 +53,7 @@ Source('system.cc')
 if env['FULL_SYSTEM']:
     Source('pseudo_inst.cc')
 else:
+    SimObject('Process.py')
+
     Source('process.cc')
     Source('syscall_emul.cc')
diff --git a/src/sim/System.py b/src/sim/System.py
new file mode 100644
index 000000000..b37e385c1
--- /dev/null
+++ b/src/sim/System.py
@@ -0,0 +1,48 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+from PhysicalMemory import *
+
+class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
+
+class System(SimObject):
+    type = 'System'
+    physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+    mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
+    if build_env['FULL_SYSTEM']:
+        boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+                                             "boot processor frequency")
+        init_param = Param.UInt64(0, "numerical value to pass into simulator")
+        boot_osflags = Param.String("a", "boot flags to pass to the kernel")
+        kernel = Param.String("", "file that contains the kernel code")
+        readfile = Param.String("", "file to read startup script from")
+        symbolfile = Param.String("", "file to get the symbols from")