arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.

--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc

5 files changed, 11 insertions, 15 deletions

diff --git a/src/sim/SConscript b/src/sim/SConscript
index 90d77848b..850af230e 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -33,9 +33,9 @@ Import('*')
 SimObject('BaseTLB.py')
 SimObject('ClockedObject.py')
 SimObject('Root.py')
-SimObject('InstTracer.py')
 SimObject('ClockDomain.py')
 SimObject('VoltageDomain.py')
+SimObject('System.py')
 
 Source('arguments.cc')
 Source('async.cc')
@@ -51,19 +51,17 @@ Source('sim_events.cc')
 Source('sim_object.cc')
 Source('simulate.cc')
 Source('stat_control.cc')
-Source('syscall_emul.cc')
 Source('clock_domain.cc')
 Source('voltage_domain.cc')
+Source('system.cc')
 
-if env['TARGET_ISA'] != 'no':
+if env['TARGET_ISA'] != 'null':
+    SimObject('InstTracer.py')
     SimObject('Process.py')
-    SimObject('System.py')
     Source('faults.cc')
     Source('process.cc')
     Source('pseudo_inst.cc')
-    Source('system.cc')
-
-if env['TARGET_ISA'] != 'no':
+    Source('syscall_emul.cc')
     Source('tlb.cc')
 
 DebugFlag('Checkpoint')
diff --git a/src/sim/arguments.hh b/src/sim/arguments.hh
index fad955999..58a43852c 100644
--- a/src/sim/arguments.hh
+++ b/src/sim/arguments.hh
@@ -33,7 +33,6 @@
 
 #include <cassert>
 
-#include "arch/vtophys.hh"
 #include "base/refcnt.hh"
 #include "base/types.hh"
 #include "mem/fs_translating_port_proxy.hh"
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 5429861d6..7a8d48ae2 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -52,13 +52,7 @@
 #include "base/hostinfo.hh"
 #include "base/statistics.hh"
 #include "base/time.hh"
-#include "config/the_isa.hh"
-#if THE_ISA == NO_ISA
-#include "arch/noisa/cpu_dummy.hh"
-#else
 #include "cpu/base.hh"
-#endif
-
 #include "sim/eventq_impl.hh"
 #include "sim/stat_control.hh"
 
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 24f9dfbad..7de483216 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -48,7 +48,6 @@
 #include "arch/isa_traits.hh"
 #include "arch/remote_gdb.hh"
 #include "arch/utility.hh"
-#include "arch/vtophys.hh"
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
 #include "base/str.hh"
@@ -228,6 +227,7 @@ System::registerThreadContext(ThreadContext *tc, int assigned)
     threadContexts[id] = tc;
     _numContexts++;
 
+#if THE_ISA != NULL_ISA
     int port = getRemoteGDBPort();
     if (port) {
         RemoteGDB *rgdb = new RemoteGDB(this, tc);
@@ -243,6 +243,7 @@ System::registerThreadContext(ThreadContext *tc, int assigned)
 
         remoteGDB[id] = rgdb;
     }
+#endif
 
     activeCpus.push_back(false);
 
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 5058e7b26..5b166eabf 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -184,7 +184,9 @@ class System : public MemObject
      */
     unsigned int cacheLineSize() const { return _cacheLineSize; }
 
+#if THE_ISA != NULL_ISA
     PCEventQueue pcEventQueue;
+#endif
 
     std::vector<ThreadContext *> threadContexts;
     int _numContexts;
@@ -380,11 +382,13 @@ class System : public MemObject
     {
         Addr addr = 0; // initialize only to avoid compiler warning
 
+#if THE_ISA != NULL_ISA
         if (symtab->findAddress(lbl, addr)) {
             T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr),
                           std::forward<Args>(args)...);
             return ev;
         }
+#endif
 
         return NULL;
     }