Merge zizzer:/bk/newmem

into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069

1 files changed, 14 insertions, 8 deletions

diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 537bfb918..fa65b08af 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -120,10 +120,22 @@ class Event : public Serializable, public FastAlloc
     /// priority; these values are used to control events that need to
     /// be ordered within a cycle.
     enum Priority {
-        /// Breakpoints should happen before anything else, so we
-        /// don't miss any action when debugging.
+        /// If we enable tracing on a particular cycle, do that as the
+        /// very first thing so we don't miss any of the events on
+        /// that cycle (even if we enter the debugger).
+        Trace_Enable_Pri        = -101,
+
+        /// Breakpoints should happen before anything else (except
+        /// enabling trace output), so we don't miss any action when
+        /// debugging.
         Debug_Break_Pri		= -100,
 
+        /// CPU switches schedule the new CPU's tick event for the
+        /// same cycle (after unscheduling the old CPU's tick event).
+        /// The switch needs to come before any tick events to make
+        /// sure we don't tick both CPUs in the same cycle.
+        CPU_Switch_Pri		=   -31,
+
         /// For some reason "delayed" inter-cluster writebacks are
         /// scheduled before regular writebacks (which have default
         /// priority).  Steve?
@@ -132,12 +144,6 @@ class Event : public Serializable, public FastAlloc
         /// Default is zero for historical reasons.
         Default_Pri		=    0,
 
-        /// CPU switches schedule the new CPU's tick event for the
-        /// same cycle (after unscheduling the old CPU's tick event).
-        /// The switch needs to come before any tick events to make
-        /// sure we don't tick both CPUs in the same cycle.
-        CPU_Switch_Pri		=   -31,
-
         /// Serailization needs to occur before tick events also, so
         /// that a serialize/unserialize is identical to an on-line
         /// CPU switch.