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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
| commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
| tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/sim | |
| parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
| download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz | |
revert 5af8f40d8f2c
Diffstat (limited to 'src/sim')
| -rw-r--r-- | src/sim/insttracer.hh | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh index 3c954df26..6819c2199 100644 --- a/src/sim/insttracer.hh +++ b/src/sim/insttracer.hh @@ -58,8 +58,6 @@ namespace Trace { class InstRecord { protected: - typedef TheISA::VectorReg VectorReg; - Tick when; // The following fields are initialized by the constructor and @@ -99,7 +97,6 @@ class InstRecord union { uint64_t as_int; double as_double; - VectorReg as_vector; } data; /** @defgroup fetch_seq @@ -123,8 +120,7 @@ class InstRecord DataInt16 = 2, DataInt32 = 4, DataInt64 = 8, - DataDouble = 3, - DataVector = sizeof(VectorReg), + DataDouble = 3 } data_status; /** @ingroup memory @@ -177,8 +173,6 @@ class InstRecord void setData(int8_t d) { setData((uint8_t)d); } void setData(double d) { data.as_double = d; data_status = DataDouble; } - void setData(const VectorReg& v) - { data.as_vector = v; data_status = DataVector; } void setFetchSeq(InstSeqNum seq) { fetch_seq = seq; fetch_seq_valid = true; } @@ -204,7 +198,6 @@ class InstRecord uint64_t getIntData() const { return data.as_int; } double getFloatData() const { return data.as_double; } - const VectorReg &getVectorData() const { return data.as_vector; } int getDataStatus() const { return data_status; } InstSeqNum getFetchSeq() const { return fetch_seq; } |