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authorAndreas Hansson <andreas.hansson@arm.com>2014-10-16 05:49:44 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-10-16 05:49:44 -0400
commit247586274724ea9f2a22a87747c9e074870d16a8 (patch)
tree0de83b50fe2856e3bc43eb9a24e2f767719ee2d5 /src/sim
parentdf973abef3a70074971375cfe52c46f53528c00e (diff)
downloadgem5-247586274724ea9f2a22a87747c9e074870d16a8.tar.xz
arch,x86,mem: Dynamically determine the ISA for Ruby store check
This patch makes the memory system ISA-agnostic by enabling the Ruby Sequencer to dynamically determine if it has to do a store check. To enable this check, the ISA is encoded as an enum, and the system is able to provide the ISA to the Sequencer at run time. --HG-- rename : src/arch/x86/insts/microldstop.hh => src/arch/x86/ldstflags.hh
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/system.hh5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/sim/system.hh b/src/sim/system.hh
index d82978018..595892385 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -271,6 +271,11 @@ class System : public MemObject
*/
bool isMemAddr(Addr addr) const;
+ /**
+ * Get the architecture.
+ */
+ Arch getArch() const { return Arch::TheISA; }
+
/**
* Get the page bytes for the ISA.
*/