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author | Sascha Bischoff <sascha.bischoff@ARM.com> | 2016-04-01 16:22:44 +0100 |
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committer | Sascha Bischoff <sascha.bischoff@ARM.com> | 2016-04-01 16:22:44 +0100 |
commit | ebc9e1d426f7dbe13b63d87afbdf8507265f8040 (patch) | |
tree | 5bab225aa545b1dda8255d560d825eb5c1ec9451 /src/sim | |
parent | f948f9fca987b25ef0716e87fdc4e874fb607c14 (diff) | |
download | gem5-ebc9e1d426f7dbe13b63d87afbdf8507265f8040.tar.xz |
sim: Fix clock_domain unserialization
This patch addresses an issue with the unserialization of clock
domains. Previously, the previous performance level was not restored
due to a bug in the code, which detected the post-unserialize update
as superfluous. This patch splits the setting of the clock domain into
two parts. The original interface of perfLevel is retained, but the
actual update takes place in signalPerfLevelUpdate, which is private
to the class. The perfLevel method checks that if the new performance
level is different to the previous performance level, and will only
call signalPerfLevelUpdate if there is a change. Therefore, the
performance level is only updated, and voltage domains notified, if
there is an actual change. The split functionality allows
signalPerfLevelUpdate to be called by startup() to explicitly force an
update post unserialization.
Diffstat (limited to 'src/sim')
-rw-r--r-- | src/sim/clock_domain.cc | 7 | ||||
-rw-r--r-- | src/sim/clock_domain.hh | 5 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/sim/clock_domain.cc b/src/sim/clock_domain.cc index 60c688b1a..1ccee7f1d 100644 --- a/src/sim/clock_domain.cc +++ b/src/sim/clock_domain.cc @@ -147,6 +147,11 @@ SrcClockDomain::perfLevel(PerfLevel perf_level) _perfLevel = perf_level; + signalPerfLevelUpdate(); +} + +void SrcClockDomain::signalPerfLevelUpdate() +{ // Signal the voltage domain that we have changed our perf level so that the // voltage domain can recompute its performance level voltageDomain()->sanitiseVoltages(); @@ -174,7 +179,7 @@ SrcClockDomain::startup() { // Perform proper clock update when all related components have been // created (i.e. after unserialization / object creation) - perfLevel(_perfLevel); + signalPerfLevelUpdate(); } SrcClockDomain * diff --git a/src/sim/clock_domain.hh b/src/sim/clock_domain.hh index 71627434a..6ba8b6396 100644 --- a/src/sim/clock_domain.hh +++ b/src/sim/clock_domain.hh @@ -244,6 +244,11 @@ class SrcClockDomain : public ClockDomain private: /** + * Inform other components about the changed performance level + */ + void signalPerfLevelUpdate(); + + /** * List of possible frequency operational points, should be in * descending order * An empty list corresponds to default frequency specified for its |