MEM: Introduce the master/slave port sub-classes in C++

This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.

3 files changed, 20 insertions, 21 deletions

diff --git a/src/sim/system.cc b/src/sim/system.cc
index 4601d2d52..2c5d4e44b 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -174,11 +174,11 @@ System::init()
         panic("System port on %s is not connected.\n", name());
 }
 
-Port*
-System::getPort(const std::string &if_name, int idx)
+MasterPort&
+System::getMasterPort(const std::string &if_name, int idx)
 {
     // no need to distinguish at the moment (besides checking)
-    return &_systemPort;
+    return _systemPort;
 }
 
 void
diff --git a/src/sim/system.hh b/src/sim/system.hh
index dd122161d..d5e45fa0d 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -78,7 +78,7 @@ class System : public MemObject
      * master for debug access and for non-structural entities that do
      * not have a port of their own.
      */
-    class SystemPort : public Port
+    class SystemPort : public MasterPort
     {
       public:
 
@@ -86,22 +86,16 @@ class System : public MemObject
          * Create a system port with a name and an owner.
          */
         SystemPort(const std::string &_name, MemObject *_owner)
-            : Port(_name, _owner)
+            : MasterPort(_name, _owner)
         { }
         bool recvTiming(PacketPtr pkt)
         { panic("SystemPort does not receive timing!\n"); return false; }
+        void recvRetry()
+        { panic("SystemPort does not expect retry!\n"); }
         Tick recvAtomic(PacketPtr pkt)
         { panic("SystemPort does not receive atomic!\n"); return 0; }
         void recvFunctional(PacketPtr pkt)
         { panic("SystemPort does not receive functional!\n"); }
-
-        /**
-         * The system port is a master port connected to a single
-         * slave and thus do not care about what ranges the slave
-         * covers (as there is nothing to choose from).
-         */
-        void recvRangeChange() { }
-
     };
 
     SystemPort _systemPort;
@@ -122,12 +116,12 @@ class System : public MemObject
      *
      * @return a reference to the system port we own
      */
-    Port& getSystemPort() { return _systemPort; }
+    MasterPort& getSystemPort() { return _systemPort; }
 
     /**
      * Additional function to return the Port of a memory object.
      */
-    Port *getPort(const std::string &if_name, int idx = -1);
+    MasterPort& getMasterPort(const std::string &if_name, int idx = -1);
 
     static const char *MemoryModeStrings[3];
 
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index 253f12072..379cdd343 100644
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -49,8 +49,7 @@
 #include "sim/sim_object.hh"
 
 class ThreadContext;
-class Packet;
-class Port;
+class MasterPort;
 
 class BaseTLB : public SimObject
 {
@@ -65,10 +64,16 @@ class BaseTLB : public SimObject
   public:
     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
 
-    /** Get any port that the TLB or hardware table walker needs.
-     * This is used for migrating port connections during a takeOverFrom()
-     * call. */
-    virtual Port*  getPort() { return NULL; }
+    /**
+     * Get the table walker master port if present. This is used for
+     * migrating port connections during a CPU takeOverFrom()
+     * call. For architectures that do not have a table walker, NULL
+     * is returned, hence the use of a pointer rather than a
+     * reference.
+     *
+     * @return A pointer to the walker master port or NULL if not present
+     */
+    virtual MasterPort* getMasterPort() { return NULL; }
 
     class Translation
     {