CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.

2 files changed, 25 insertions, 0 deletions

diff --git a/src/sim/tlb.cc b/src/sim/tlb.cc
index f7b57cbbc..e82e4f277 100644
--- a/src/sim/tlb.cc
+++ b/src/sim/tlb.cc
@@ -50,6 +50,14 @@ GenericTLB::translateAtomic(RequestPtr req, ThreadContext * tc, bool)
 }
 
 void
+GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
+void
 GenericTLB::demapPage(Addr vaddr, uint64_t asn)
 {
     warn("Demapping pages in the generic TLB is unnecessary.\n");
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index 8429c0df5..8893f8c97 100644
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -47,6 +47,21 @@ class BaseTLB : public SimObject
 
   public:
     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
+
+    class Translation
+    {
+      public:
+        virtual ~Translation()
+        {}
+
+        /*
+         * The memory for this object may be dynamically allocated, and it may
+         * be responsible for cleaning itself up which will happen in this
+         * function. Once it's called, the object is no longer valid.
+         */
+        virtual void finish(Fault fault, RequestPtr req,
+                ThreadContext *tc, bool write=false) = 0;
+    };
 };
 
 class GenericTLB : public BaseTLB
@@ -59,6 +74,8 @@ class GenericTLB : public BaseTLB
     void demapPage(Addr vaddr, uint64_t asn);
 
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool=false);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, bool=false);
 };
 
 #endif // __ARCH_SPARC_TLB_HH__