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authorNathan Binkert <nate@binkert.org>2009-05-17 14:34:52 -0700
committerNathan Binkert <nate@binkert.org>2009-05-17 14:34:52 -0700
commit8d2e51c7f52670055ffe97e221302561b87015a2 (patch)
tree792d211d603bd9155dee00861d1ce92d3ba2f09d /src/sim
parent709d859530325f28b904001f5a55dbdec2bad199 (diff)
downloadgem5-8d2e51c7f52670055ffe97e221302561b87015a2.tar.xz
includes: sort includes again
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/arguments.hh4
-rw-r--r--src/sim/eventq.hh2
-rw-r--r--src/sim/init.cc2
-rw-r--r--src/sim/insttracer.hh2
-rw-r--r--src/sim/sim_object.cc4
-rw-r--r--src/sim/simulate.cc4
-rw-r--r--src/sim/syscall_emul.hh2
7 files changed, 10 insertions, 10 deletions
diff --git a/src/sim/arguments.hh b/src/sim/arguments.hh
index 3cef49e5d..abc3da812 100644
--- a/src/sim/arguments.hh
+++ b/src/sim/arguments.hh
@@ -31,12 +31,12 @@
#ifndef __SIM_ARGUMENTS_HH__
#define __SIM_ARGUMENTS_HH__
-#include <assert.h>
+#include <cassert>
#include "arch/vtophys.hh"
#include "base/refcnt.hh"
-#include "mem/vport.hh"
#include "base/types.hh"
+#include "mem/vport.hh"
class ThreadContext;
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 219d306f0..29efdeb6f 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -47,8 +47,8 @@
#include "base/flags.hh"
#include "base/misc.hh"
#include "base/trace.hh"
-#include "sim/serialize.hh"
#include "base/types.hh"
+#include "sim/serialize.hh"
class EventQueue; // forward declaration
diff --git a/src/sim/init.cc b/src/sim/init.cc
index 2e34740fb..1e90f1568 100644
--- a/src/sim/init.cc
+++ b/src/sim/init.cc
@@ -39,9 +39,9 @@
#include "base/cprintf.hh"
#include "base/misc.hh"
+#include "base/types.hh"
#include "sim/async.hh"
#include "sim/core.hh"
-#include "base/types.hh"
#include "sim/init.hh"
using namespace std;
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 23a0a14a6..bcab45519 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -34,9 +34,9 @@
#include "base/bigint.hh"
#include "base/trace.hh"
+#include "base/types.hh"
#include "cpu/inst_seq.hh" // for InstSeqNum
#include "cpu/static_inst.hh"
-#include "base/types.hh"
#include "sim/sim_object.hh"
class ThreadContext;
diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index 81ab00f9e..f7f539774 100644
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -29,14 +29,14 @@
* Nathan Binkert
*/
-#include <assert.h>
+#include <cassert>
#include "base/callback.hh"
#include "base/inifile.hh"
#include "base/match.hh"
#include "base/misc.hh"
-#include "base/trace.hh"
#include "base/stats/events.hh"
+#include "base/trace.hh"
#include "base/types.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index 2d3b84e09..0cc603d3f 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -31,13 +31,13 @@
#include "base/misc.hh"
#include "base/pollevent.hh"
-#include "sim/stat_control.hh"
+#include "base/types.hh"
#include "sim/async.hh"
#include "sim/eventq.hh"
-#include "base/types.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
#include "sim/simulate.hh"
+#include "sim/stat_control.hh"
/** Simulate for num_cycles additional cycles. If num_cycles is -1
* (the default), do not limit simulation; some other event must
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 4831419b0..0d5bf1723 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -50,11 +50,11 @@
#include <fcntl.h>
#include <sys/uio.h>
-#include "base/types.hh"
#include "base/chunk_generator.hh"
#include "base/intmath.hh" // for RoundUp
#include "base/misc.hh"
#include "base/trace.hh"
+#include "base/types.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/translating_port.hh"