mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.

2 files changed, 74 insertions, 0 deletions

diff --git a/src/sim/system.cc b/src/sim/system.cc
index e5e68bf89..1f7527426 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -113,6 +113,16 @@ System::System(Params *p)
         physProxy = new PortProxy(*getSystemPort());
         virtProxy = new FSTranslatingPortProxy(*getSystemPort());
     }
+
+    // Get the generic system master IDs
+    MasterID tmp_id M5_VAR_USED;
+    tmp_id = getMasterId("writebacks");
+    assert(tmp_id == Request::wbMasterId);
+    tmp_id = getMasterId("functional");
+    assert(tmp_id == Request::funcMasterId);
+    tmp_id = getMasterId("interrupt");
+    assert(tmp_id == Request::intMasterId);
+
 }
 
 System::~System()
@@ -399,6 +409,42 @@ printSystems()
     System::printSystems();
 }
 
+MasterID
+System::getMasterId(std::string master_name)
+{
+    // strip off system name if the string starts with it
+    if (master_name.size() > name().size() &&
+                          master_name.compare(0, name().size(), name()) == 0)
+        master_name = master_name.erase(0, name().size() + 1);
+
+    // CPUs in switch_cpus ask for ids again after switching
+    for (int i = 0; i < masterIds.size(); i++) {
+        if (masterIds[i] == master_name) {
+            return i;
+        }
+    }
+
+    // todo: Check if stats are enabled yet
+    // I just don't know a good way to do it
+
+    if (false)
+        fatal("Can't request a masterId after regStats(). \
+                You must do so in init().\n");
+
+    masterIds.push_back(master_name);
+
+    return masterIds.size() - 1;
+}
+
+std::string
+System::getMasterName(MasterID master_id)
+{
+    if (master_id >= masterIds.size())
+        fatal("Invalid master_id passed to getMasterName()\n");
+
+    return masterIds[master_id];
+}
+
 const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
     "timing"};
 
diff --git a/src/sim/system.hh b/src/sim/system.hh
index eb192fb99..9d11132e5 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -229,7 +229,35 @@ class System : public MemObject
     uint32_t numWorkIds;
     std::vector<bool> activeCpus;
 
+    /** This array is a per-sytem list of all devices capable of issuing a
+     * memory system request and an associated string for each master id.
+     * It's used to uniquely id any master in the system by name for things
+     * like cache statistics.
+     */
+    std::vector<std::string> masterIds;
+
   public:
+
+    /** Request an id used to create a request object in the system. All objects
+     * that intend to issues requests into the memory system must request an id
+     * in the init() phase of startup. All master ids must be fixed by the
+     * regStats() phase that immediately preceeds it. This allows objects in the
+     * memory system to understand how many masters may exist and
+     * appropriately name the bins of their per-master stats before the stats
+     * are finalized
+     */
+    MasterID getMasterId(std::string req_name);
+
+    /** Get the name of an object for a given request id.
+     */
+    std::string getMasterName(MasterID master_id);
+
+    /** Get the number of masters registered in the system */
+    MasterID maxMasters()
+    {
+        return masterIds.size();
+    }
+
     virtual void regStats();
     /**
      * Called by pseudo_inst to track the number of work items started by this