summaryrefslogtreecommitdiff
path: root/src/sim
diff options
context:
space:
mode:
authorAlexandru Dutu <alexandru.dutu@amd.com>2014-11-23 18:01:09 -0800
committerAlexandru Dutu <alexandru.dutu@amd.com>2014-11-23 18:01:09 -0800
commit1f539f13c32ad5a9187d56a098d4c857639b0e05 (patch)
tree7618c3b946d9c25d9b22018f226eee77b6de4aaf /src/sim
parentc11bcb8119273ef91c40a25b8fd9471a887d0ee5 (diff)
downloadgem5-1f539f13c32ad5a9187d56a098d4c857639b0e05.tar.xz
mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes.
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/Process.py2
-rw-r--r--src/sim/process.cc7
-rw-r--r--src/sim/process.hh10
3 files changed, 10 insertions, 9 deletions
diff --git a/src/sim/Process.py b/src/sim/Process.py
index f64ab0883..ca9aaf5b1 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -45,7 +45,7 @@ class Process(SimObject):
@classmethod
def export_methods(cls, code):
- code('bool map(Addr vaddr, Addr paddr, int size);')
+ code('bool map(Addr vaddr, Addr paddr, int size, bool cacheable=true);')
class EmulatedDriver(SimObject):
type = 'EmulatedDriver'
diff --git a/src/sim/process.cc b/src/sim/process.cc
index f53c6b850..0412c27e0 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -338,7 +338,7 @@ Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
{
int npages = divCeil(size, (int64_t)PageBytes);
Addr paddr = system->allocPhysPages(npages);
- pTable->map(vaddr, paddr, size, clobber);
+ pTable->map(vaddr, paddr, size, clobber ? PageTableBase::Clobber : 0);
}
bool
@@ -553,9 +553,10 @@ Process::unserialize(Checkpoint *cp, const std::string &section)
bool
-Process::map(Addr vaddr, Addr paddr, int size)
+Process::map(Addr vaddr, Addr paddr, int size, bool cacheable)
{
- pTable->map(vaddr, paddr, size);
+ pTable->map(vaddr, paddr, size,
+ cacheable ? 0 : PageTableBase::Uncacheable);
return true;
}
diff --git a/src/sim/process.hh b/src/sim/process.hh
index d0865f990..85ac8a1d5 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -219,19 +219,19 @@ class Process : public SimObject
bool fixupStackFault(Addr vaddr);
/**
- * Map a contiguous range of virtual addresses in this process's
+ * Maps a contiguous range of virtual addresses in this process's
* address space to a contiguous range of physical addresses.
- * This function exists primarily to enable exposing the map
- * operation to python, so that configuration scripts can set up
- * mappings in SE mode.
+ * This function exists primarily to expose the map operation to
+ * python, so that configuration scripts can set up mappings in SE mode.
*
* @param vaddr The starting virtual address of the range.
* @param paddr The starting physical address of the range.
* @param size The length of the range in bytes.
+ * @param cacheable Specifies whether accesses are cacheable.
* @return True if the map operation was successful. (At this
* point in time, the map operation always succeeds.)
*/
- bool map(Addr vaddr, Addr paddr, int size);
+ bool map(Addr vaddr, Addr paddr, int size, bool cacheable = true);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);