sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.

6 files changed, 7 insertions, 4 deletions

diff --git a/src/sim/BaseTLB.py b/src/sim/BaseTLB.py
index 9aca4a97c..8a03413a9 100644
--- a/src/sim/BaseTLB.py
+++ b/src/sim/BaseTLB.py
@@ -31,3 +31,4 @@ from m5.SimObject import SimObject
 class BaseTLB(SimObject):
     type = 'BaseTLB'
     abstract = True
+    cxx_header = "sim/tlb.hh"
diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py
index 26b0e2348..8bc4031a4 100644
--- a/src/sim/ClockedObject.py
+++ b/src/sim/ClockedObject.py
@@ -42,6 +42,7 @@ from m5.proxy import *
 class ClockedObject(SimObject):
     type = 'ClockedObject'
     abstract = True
+    cxx_header = "sim/clocked_object.hh"
 
     # Clock period of this object, with the default value being the
     # clock period of the parent object, unproxied at instantiation
diff --git a/src/sim/InstTracer.py b/src/sim/InstTracer.py
index 9ba91a019..7405ecbc6 100644
--- a/src/sim/InstTracer.py
+++ b/src/sim/InstTracer.py
@@ -33,3 +33,4 @@ class InstTracer(SimObject):
     type = 'InstTracer'
     cxx_class = 'Trace::InstTracer'
     abstract = True
+    cxx_header = "sim/insttracer.hh"
diff --git a/src/sim/Process.py b/src/sim/Process.py
index bb76b5cf7..55ccc50d0 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -33,6 +33,7 @@ from m5.proxy import *
 class Process(SimObject):
     type = 'Process'
     abstract = True
+    cxx_header = "sim/process.hh"
     input = Param.String('cin', "filename for stdin")
     output = Param.String('cout', 'filename for stdout')
     errout = Param.String('cerr', 'filename for stderr')
@@ -40,15 +41,12 @@ class Process(SimObject):
     max_stack_size = Param.MemorySize('64MB', 'maximum size of the stack')
 
     @classmethod
-    def export_method_cxx_predecls(cls, code):
-        code('#include "sim/process.hh"')
-
-    @classmethod
     def export_methods(cls, code):
         code('bool map(Addr vaddr, Addr paddr, int size);')
 
 class LiveProcess(Process):
     type = 'LiveProcess'
+    cxx_header = "sim/process.hh"
     executable = Param.String('', "executable (overrides cmd[0] if set)")
     cmd = VectorParam.String("command line (executable plus arguments)")
     env = VectorParam.String([], "environment settings")
diff --git a/src/sim/Root.py b/src/sim/Root.py
index daa0a903f..44f768c0b 100644
--- a/src/sim/Root.py
+++ b/src/sim/Root.py
@@ -58,6 +58,7 @@ class Root(SimObject):
         return 'root'
 
     type = 'Root'
+    cxx_header = "sim/root.hh"
 
     full_system = Param.Bool("if this is a full system simulation")
 
diff --git a/src/sim/System.py b/src/sim/System.py
index 92883b299..3d45c23c0 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -39,6 +39,7 @@ class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
 
 class System(MemObject):
     type = 'System'
+    cxx_header = "sim/system.hh"
     system_port = MasterPort("System port")
 
     # Override the clock from the ClockedObject which looks at the