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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-10-23 10:49:38 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-15 14:16:57 +0000 |
| commit | ccdbc394e2f4adcb8a3b89b8df7ce403b9fbd937 (patch) | |
| tree | 50572b3a0346812c9dbf8aa7799d0649f38d18a8 /src/sim | |
| parent | 053bb85b3220986f56fbbd24bd5bc7c04dea4ce6 (diff) | |
| download | gem5-ccdbc394e2f4adcb8a3b89b8df7ce403b9fbd937.tar.xz | |
arch-arm: Writes to DCCMVAC shouldn't flush pipeline
Writes to DCCMVAC (Data Cache line Clean by VA to PoC) system register
shouldn't flush the pipeline as a result of the operation. This addition
was wrongly introduced for supporting self-modifying code. Software
barriers should be used instead.
Change-Id: Idf0c27d2e49ca01be19888ae5523b8f8eaefa7b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5362
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/sim')
0 files changed, 0 insertions, 0 deletions