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| author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-10-16 16:04:08 +0100 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-01-30 16:57:54 +0000 |
| commit | 25474167e5b247d1b91fbf802c5b396a63ae705e (patch) | |
| tree | b509597b23d792734f55c33b8125eebfbd9cd3a5 /src/sim | |
| parent | c6f5db8743f19b02a38146d9cf2a829883387008 (diff) | |
| download | gem5-25474167e5b247d1b91fbf802c5b396a63ae705e.tar.xz | |
arch,cpu: Add vector predicate registers
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.
Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/sim')
| -rw-r--r-- | src/sim/insttracer.hh | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh index d57f5a04d..c1efd2118 100644 --- a/src/sim/insttracer.hh +++ b/src/sim/insttracer.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 ARM Limited + * Copyright (c) 2014, 2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -44,6 +44,8 @@ #ifndef __INSTRECORD_HH__ #define __INSTRECORD_HH__ +#include "arch/generic/vec_pred_reg.hh" +#include "arch/generic/vec_reg.hh" #include "base/types.hh" #include "cpu/inst_seq.hh" #include "cpu/static_inst.hh" @@ -95,6 +97,9 @@ class InstRecord union { uint64_t as_int; double as_double; + ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec; + ::VecPredRegContainer<TheISA::VecPredRegSizeBits, + TheISA::VecPredRegHasPackedRepr>* as_pred; } data; /** @defgroup fetch_seq @@ -118,7 +123,9 @@ class InstRecord DataInt16 = 2, DataInt32 = 4, DataInt64 = 8, - DataDouble = 3 + DataDouble = 3, + DataVec = 5, + DataVecPred = 6 } data_status; /** @ingroup memory @@ -150,7 +157,16 @@ class InstRecord fetch_seq_valid(false), cp_seq_valid(false), predicate(true) { } - virtual ~InstRecord() { } + virtual ~InstRecord() + { + if (data_status == DataVec) { + assert(data.as_vec); + delete data.as_vec; + } else if (data_status == DataVecPred) { + assert(data.as_pred); + delete data.as_pred; + } + } void setWhen(Tick new_when) { when = new_when; } void setMem(Addr a, Addr s, unsigned f) @@ -181,6 +197,22 @@ class InstRecord void setData(double d) { data.as_double = d; data_status = DataDouble; } + void + setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d) + { + data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d); + data_status = DataVec; + } + + void + setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits, + TheISA::VecPredRegHasPackedRepr>& d) + { + data.as_pred = new ::VecPredRegContainer< + TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr>(d); + data_status = DataVecPred; + } + void setFetchSeq(InstSeqNum seq) { fetch_seq = seq; fetch_seq_valid = true; } |