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authorGabe Black <gabeblack@google.com>2019-11-25 02:26:51 -0800
committerGabe Black <gabeblack@google.com>2019-12-10 23:58:14 +0000
commit390a74f59934b85d91489f8a563450d8321b602d (patch)
treec5a31b56a74e888c61f0645349b58535d2eae26a /src/sim
parentcb3457ccd17a89a4df3e70d35e0254c77a0b5782 (diff)
downloadgem5-390a74f59934b85d91489f8a563450d8321b602d.tar.xz
sim,arch: Collapse the ISA specific versions of m5Syscall.
The x86 version doesn't do anything x86 specific, and so can be used generically in sim/pseudo_inst.(hh|cc) Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/pseudo_inst.cc12
-rw-r--r--src/sim/pseudo_inst.hh1
2 files changed, 13 insertions, 0 deletions
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 92886dacb..53892b5d1 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -586,6 +586,18 @@ switchcpu(ThreadContext *tc)
exitSimLoop("switchcpu");
}
+/*
+ * This function is executed when the simulation is executing the syscall
+ * handler in System Emulation mode.
+ */
+void
+m5Syscall(ThreadContext *tc)
+{
+ DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n");
+ Fault fault;
+ tc->syscall(&fault);
+}
+
void
togglesync(ThreadContext *tc)
{
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index d9b981f94..977ed1d39 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -88,6 +88,7 @@ void debugbreak(ThreadContext *tc);
void switchcpu(ThreadContext *tc);
void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
+void m5Syscall(ThreadContext *tc);
void togglesync(ThreadContext *tc);
} // namespace PseudoInst