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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-15 10:20:44 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-26 09:29:53 +0000 |
| commit | b90fcd7357dfc065908e60def2b9c18c1a091627 (patch) | |
| tree | 66805a898b300a3dabf84d13bb5bb9d49016cd1e /src/sim | |
| parent | 579c2cd54b1b29e8283f789a5bb221edb53e6f83 (diff) | |
| download | gem5-b90fcd7357dfc065908e60def2b9c18c1a091627.tar.xz | |
dev-arm: Fix GITS_BASER initialization/access
The patch is fixing/improving GITS_BASER registers initialization.
* Not using reserved table types anymore (GITS_BASER.TYPE)
* Using write mask for handling WI bits
Change-Id: Ibe24667fdf22b42b86496167c19fc00bbb0ba191
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20328
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/sim')
0 files changed, 0 insertions, 0 deletions