arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 files changed, 55 insertions, 7 deletions

diff --git a/src/sim/SConscript b/src/sim/SConscript
index a59b0ed1a..54e251287 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -55,6 +55,7 @@ Source('init.cc', add_tags='python')
 Source('init_signals.cc')
 Source('main.cc', tags='main')
 Source('port.cc')
+Source('python.cc', add_tags='python')
 Source('root.cc')
 Source('serialize.cc')
 Source('drain.cc')
diff --git a/src/sim/cxx_manager.cc b/src/sim/cxx_manager.cc
index 915736127..35d008d58 100644
--- a/src/sim/cxx_manager.cc
+++ b/src/sim/cxx_manager.cc
@@ -471,9 +471,9 @@ CxxConfigManager::bindPort(
      *  getCxxConfigDirectoryEntry for each object. */
 
     /* It would be nice to be able to catch the errors from these calls. */
-    BaseMasterPort &master_port = master_mem_object->getMasterPort(
+    Port &master_port = master_mem_object->getPort(
         master_port_name, master_port_index);
-    BaseSlavePort &slave_port = slave_mem_object->getSlavePort(
+    Port &slave_port = slave_mem_object->getPort(
         slave_port_name, slave_port_index);
 
     if (master_port.isConnected()) {
diff --git a/src/sim/init.cc b/src/sim/init.cc
index 5a49f360a..1fb7e6e1d 100644
--- a/src/sim/init.cc
+++ b/src/sim/init.cc
@@ -207,7 +207,6 @@ EmbeddedPyBind::initAll()
     pybind_init_debug(m_m5);
 
     pybind_init_event(m_m5);
-    pybind_init_pyobject(m_m5);
     pybind_init_stats(m_m5);
 
     for (auto &kv : getMap()) {
diff --git a/src/sim/python.cc b/src/sim/python.cc
new file mode 100644
index 000000000..159f32a8a
--- /dev/null
+++ b/src/sim/python.cc
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2019 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "pybind11/pybind11.h"
+#include "sim/init.hh"
+#include "sim/port.hh"
+
+namespace
+{
+
+void
+sim_pybind(pybind11::module &m_internal)
+{
+    pybind11::module m = m_internal.def_submodule("sim");
+    pybind11::class_<
+        Port, std::unique_ptr<Port, pybind11::nodelete>>(m, "Port")
+        .def("bind", &Port::bind)
+        ;
+}
+EmbeddedPyBind embed_("sim", &sim_pybind);
+
+} // anonymous namespace
diff --git a/src/sim/system.cc b/src/sim/system.cc
index ffa8edaa6..2113fc079 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -218,8 +218,8 @@ System::init()
         panic("System port on %s is not connected.\n", name());
 }
 
-BaseMasterPort&
-System::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+System::getPort(const std::string &if_name, PortID idx)
 {
     // no need to distinguish at the moment (besides checking)
     return _systemPort;
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 878c81252..69448d35f 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -128,8 +128,8 @@ class System : public MemObject
     /**
      * Additional function to return the Port of a memory object.
      */
-    BaseMasterPort& getMasterPort(const std::string &if_name,
-                                  PortID idx = InvalidPortID) override;
+    Port &getPort(const std::string &if_name,
+                  PortID idx=InvalidPortID) override;
 
     /** @{ */
     /**