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authorGabe Black <gabeblack@google.com>2019-03-12 00:33:52 -0700
committerGabe Black <gabeblack@google.com>2019-03-19 10:23:12 +0000
commitdee6fe7b6a4ce4f2d1e08af9250b6d1d6ce96836 (patch)
treec16ccab67f329f37c4b8a9abd8d06ee4ed015786 /src/systemc/core/SystemC.py
parentd3d24835bcc03ecf312ac6ba7df114656770730f (diff)
downloadgem5-dee6fe7b6a4ce4f2d1e08af9250b6d1d6ce96836.tar.xz
systemc: Hook up gem5_getPort to the gem5 getPort mechanism.
Change-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/systemc/core/SystemC.py')
-rw-r--r--src/systemc/core/SystemC.py6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/systemc/core/SystemC.py b/src/systemc/core/SystemC.py
index 649d6d367..74b7cec14 100644
--- a/src/systemc/core/SystemC.py
+++ b/src/systemc/core/SystemC.py
@@ -25,7 +25,7 @@
#
# Authors: Gabe Black
-from m5.SimObject import SimObject
+from m5.SimObject import SimObject, cxxMethod
# This class represents the systemc kernel. There should be exactly one in the
# simulation. It receives gem5 SimObject lifecycle callbacks (init, regStats,
@@ -62,6 +62,10 @@ class SystemC_ScModule(SystemC_ScObject):
cxx_class = 'sc_core::sc_module'
cxx_header = 'systemc/ext/core/sc_module.hh'
+ @cxxMethod(return_value_policy="reference", cxx_name="gem5_getPort")
+ def getPort(self, if_name, iex):
+ return None
+
try:
import _m5
except: