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| author | Daniel R. Carvalho <odanrc@yahoo.com.br> | 2018-12-04 13:23:18 +0100 |
|---|---|---|
| committer | Daniel Carvalho <odanrc@yahoo.com.br> | 2019-03-07 13:07:09 +0000 |
| commit | 97281129c9b24ce51d4c9ad2f5bba4b15c375e14 (patch) | |
| tree | ccb4137833e783b988a562fc1fdab8dc2c36154a /src/systemc/python/systemc.py | |
| parent | 6c00d57cce58973094e9cacd1bf3431a3407e866 (diff) | |
| download | gem5-97281129c9b24ce51d4c9ad2f5bba4b15c375e14.tar.xz | |
mem-cache: Use header delay on latency calculation
Previously the bus delay was being ignored for the access latency
calculation, and then applied on top of the access latency. This
patch fixes the order, as first the packet must arrive before the
access starts.
Change-Id: I6d55299a911d54625c147814dd423bfc63ef1b65
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14876
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/systemc/python/systemc.py')
0 files changed, 0 insertions, 0 deletions