systemc: Import tests from the Accellera systemc distribution.

Change-Id: Iad76b398949a55d768a34d027a2d8e3739953da6
Reviewed-on: https://gem5-review.googlesource.com/10845
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

2 files changed, 55 insertions, 0 deletions

diff --git a/src/systemc/tests/systemc/bugs/bug_147853/bug_147853.cpp b/src/systemc/tests/systemc/bugs/bug_147853/bug_147853.cpp
new file mode 100644
index 000000000..82c20d6a3
--- /dev/null
+++ b/src/systemc/tests/systemc/bugs/bug_147853/bug_147853.cpp
@@ -0,0 +1,34 @@
+// This tests that sc_clock values are updated during the value update phase
+// not during the execution phase of a delta cycle.
+
+#include "systemc.h"
+
+
+SC_MODULE(Test) {
+  sc_in_clk clk;
+  sc_event e1;
+  sc_time d;
+
+  void main() {
+    cerr << sc_time_stamp() <<" " << name() << " clk = " << clk.read() << "\n";
+    e1.notify(d);
+  }
+  SC_CTOR(Test) :d(5,SC_NS) {
+    SC_METHOD(main);
+    sensitive << e1;
+  }
+};
+
+
+int sc_main(int argc,char *argv[]) {
+  
+  Test t1("t1");
+  sc_clock clk("clk",10,SC_NS);
+  Test t2("t2");
+  
+  t1.clk(clk);
+  t2.clk(clk);
+  
+  sc_start(50,SC_NS);
+  return 0;
+}
diff --git a/src/systemc/tests/systemc/bugs/bug_147853/golden/bug_147853.log b/src/systemc/tests/systemc/bugs/bug_147853/golden/bug_147853.log
new file mode 100644
index 000000000..cb6267fb4
--- /dev/null
+++ b/src/systemc/tests/systemc/bugs/bug_147853/golden/bug_147853.log
@@ -0,0 +1,21 @@
+SystemC Simulation
+0 s t1 clk = 0
+0 s t2 clk = 0
+5 ns t1 clk = 1
+5 ns t2 clk = 1
+10 ns t1 clk = 0
+10 ns t2 clk = 0
+15 ns t1 clk = 1
+15 ns t2 clk = 1
+20 ns t1 clk = 0
+20 ns t2 clk = 0
+25 ns t1 clk = 1
+25 ns t2 clk = 1
+30 ns t1 clk = 0
+30 ns t2 clk = 0
+35 ns t1 clk = 1
+35 ns t2 clk = 1
+40 ns t1 clk = 0
+40 ns t2 clk = 0
+45 ns t1 clk = 1
+45 ns t2 clk = 1