systemc: Import tests from the Accellera systemc distribution.

Change-Id: Iad76b398949a55d768a34d027a2d8e3739953da6
Reviewed-on: https://gem5-review.googlesource.com/10845
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

10 files changed, 853 insertions, 0 deletions

diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.cpp
new file mode 100644
index 000000000..3dc7a1980
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.cpp
@@ -0,0 +1,97 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  bitwidth.cpp -- 
+
+  Original Author: Rocco Jonack, Synopsys, Inc., 1999-12-14
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+
+#include "bitwidth.h"
+
+void bitwidth::entry(){
+
+  sc_biguint<2>     tmp1;
+  sc_biguint<2>     tmp1a;
+  sc_bigint<4>      tmp2;
+  sc_bigint<4>      tmp2a;
+  sc_biguint<6>     tmp3;
+  sc_biguint<6>     tmp3a;
+  sc_bigint<8>      tmp4;
+  sc_bigint<8>      tmp4a;
+
+  // reset_loop
+    out_valid.write(false);
+    out_ack.write(false);
+    wait();
+
+  //
+  // main loop
+  //
+  //
+  while(1) {
+    while(in_valid.read()==false) wait();
+    //reading the inputs
+    tmp1 = in_value1.read();
+    tmp2 = in_value2.read();
+    tmp3 = in_value3.read();
+    tmp4 = in_value4.read();
+
+    //execute simple operations
+    // expected bitwidth 2 2 2
+    tmp1a = tmp1 - tmp1;
+    // expected bitwidth 2 4 4
+    tmp2a = tmp2 - tmp1;
+    // expected bitwidth 6 2 6
+    tmp3a = tmp3 - tmp1;
+    // expected bitwidth 4 8 8
+    tmp4a = tmp4 - tmp2;
+   
+    out_ack.write(true);
+    wait();
+    out_ack.write(false);
+
+    // write outputs
+    out_value1.write(tmp1a);
+    out_value2.write(tmp2a);
+    out_value3.write(tmp3a);
+    out_value4.write(tmp4a);
+    out_valid.write(true);
+    wait();
+    out_valid.write(false);
+    wait();
+  }
+}
+
+// EOF
+
+
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.f
new file mode 100644
index 000000000..53a59162e
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.f
@@ -0,0 +1,4 @@
+bitwidth/stimulus.cpp
+bitwidth/display.cpp
+bitwidth/bitwidth.cpp
+bitwidth/main.cpp
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.h
new file mode 100644
index 000000000..e31268284
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.h
@@ -0,0 +1,115 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  bitwidth.h -- 
+
+  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+
+#include "common.h"
+
+SC_MODULE( bitwidth )
+{
+    SC_HAS_PROCESS( bitwidth );
+
+    sc_in_clk clk;
+
+    //====================================================================
+    // [C] Always Needed Member Function
+    //        --  constructor
+    //        --  entry
+    //====================================================================
+
+    const sc_signal<bool>&             reset ;
+    const sc_signal_bool_vector2&      in_value1;     // Input  port
+    const sc_signal_bool_vector4&      in_value2;     // Input  port
+    const sc_signal_bool_vector6&      in_value3;     // Input  port
+    const sc_signal_bool_vector8&      in_value4;     // Input  port
+    const sc_signal<bool>&             in_valid;      // Input  port
+    sc_signal_bool_vector2&            out_value1;    // Output port
+    sc_signal_bool_vector4&            out_value2;    // Output port
+    sc_signal_bool_vector6&            out_value3;    // Output port
+    sc_signal_bool_vector8&            out_value4;    // Output port
+    sc_signal<bool>&                   out_ack;       // Output port
+    sc_signal<bool>&                   out_valid;     // Output port
+
+
+    //
+    // Constructor
+    //
+
+    bitwidth (
+               sc_module_name   NAME,          // referense name
+               sc_clock&        CLK,           // clock
+        const  sc_signal<bool>& RESET,
+        const  sc_signal_bool_vector2&            IN_VALUE1,
+        const  sc_signal_bool_vector4&            IN_VALUE2,
+        const  sc_signal_bool_vector6&            IN_VALUE3,
+        const  sc_signal_bool_vector8&            IN_VALUE4,
+        const  sc_signal<bool>&                   IN_VALID,     // Input  port
+               sc_signal_bool_vector2&            OUT_VALUE1,
+               sc_signal_bool_vector4&            OUT_VALUE2,
+               sc_signal_bool_vector6&            OUT_VALUE3,
+               sc_signal_bool_vector8&            OUT_VALUE4,
+               sc_signal<bool>&                   OUT_ACK,
+               sc_signal<bool>&                   OUT_VALID    // Output port
+        )
+        : 
+          reset        (RESET),
+          in_value1    (IN_VALUE1),
+          in_value2    (IN_VALUE2),
+          in_value3    (IN_VALUE3),
+          in_value4    (IN_VALUE4),
+          in_valid     (IN_VALID),
+          out_value1   (OUT_VALUE1),
+          out_value2   (OUT_VALUE2),
+          out_value3   (OUT_VALUE3),
+          out_value4   (OUT_VALUE4),
+          out_ack      (OUT_ACK),
+          out_valid    (OUT_VALID)
+
+    {
+      clk          (CLK);
+	  SC_CTHREAD( entry, clk.pos() );
+      reset_signal_is(reset,true);
+    };
+
+    //
+
+void entry ();
+
+};
+
+// EOF
+
+
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/common.h
new file mode 100644
index 000000000..d3b94a8f8
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/common.h
@@ -0,0 +1,48 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  common.h -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#ifndef COMMON_H
+#define COMMON_H
+
+#include "systemc.h"
+
+typedef sc_signal<sc_bv<2> > sc_signal_bool_vector2;
+typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4;
+typedef sc_signal<sc_bv<6> > sc_signal_bool_vector6;
+typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8;
+
+#endif
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.cpp
new file mode 100644
index 000000000..e6d9371f1
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  display.cpp -- 
+
+  Original Author: Rocco Jonack, Synopsys, Inc., 1999-12-10
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+
+#include "display.h"
+
+void display::entry() {
+ 
+    int counter = 0;
+    while(counter<100){
+       do { wait(); } while ( in_valid == false);
+       cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << endl;
+       do { wait(); } while ( in_valid == true);
+       counter++;
+    }
+    sc_stop();
+}
+// EOF
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.h
new file mode 100644
index 000000000..00498390d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  display.h -- 
+
+  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+
+#include "common.h"
+
+SC_MODULE( display )
+{
+    SC_HAS_PROCESS( display );
+
+    sc_in_clk clk;
+
+    const sc_signal_bool_vector2&      in_value1;     // Input  port
+    const sc_signal_bool_vector4&      in_value2;     // Input  port
+    const sc_signal_bool_vector6&      in_value3;     // Input  port
+    const sc_signal_bool_vector8&      in_value4;     // Input  port
+    const sc_signal<bool>&             in_valid;                         // Input  port
+
+   // 
+   // Constructor
+   //
+
+   display(
+               sc_module_name    NAME,      // reference name
+               sc_clock&      CLK,          // clock
+               const sc_signal_bool_vector2&     IN_VALUE1,
+               const sc_signal_bool_vector4&     IN_VALUE2,
+               const sc_signal_bool_vector6&     IN_VALUE3,
+               const sc_signal_bool_vector8&     IN_VALUE4,
+               const sc_signal<bool>&            IN_VALID
+           ) 
+           : 
+             in_value1    (IN_VALUE1),
+             in_value2    (IN_VALUE2),
+             in_value3    (IN_VALUE3),
+             in_value4    (IN_VALUE4),
+             in_valid     (IN_VALID)
+     {
+       clk          (CLK);
+	   SC_CTHREAD( entry, clk.pos() );
+     };
+
+ 
+ void entry();
+};
+
+// EOF
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/golden/bitwidth.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/golden/bitwidth.log
new file mode 100644
index 000000000..26dab71e7
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/golden/bitwidth.log
@@ -0,0 +1,204 @@
+SystemC Simulation
+Stimuli: 0 1 2 3
+Stimuli: 1 2 3 4
+Display: 00 0001 000010 00000010
+Stimuli: -2 3 4 5
+Display: 00 0001 000010 00000010
+Stimuli: -1 4 5 6
+Display: 00 0001 000010 00000010
+Stimuli: 0 5 6 7
+Display: 00 0001 000010 00000010
+Stimuli: 1 6 7 8
+Display: 00 0101 000110 00000010
+Stimuli: -2 7 8 9
+Display: 00 0101 000110 00000010
+Stimuli: -1 -8 9 10
+Display: 00 0101 000110 00000010
+Stimuli: 0 -7 10 11
+Display: 00 0101 000110 00010010
+Stimuli: 1 -6 11 12
+Display: 00 1001 001010 00010010
+Stimuli: -2 -5 12 13
+Display: 00 1001 001010 00010010
+Stimuli: -1 -4 13 14
+Display: 00 1001 001010 00010010
+Stimuli: 0 -3 14 15
+Display: 00 1001 001010 00010010
+Stimuli: 1 -2 15 16
+Display: 00 1101 001110 00010010
+Stimuli: -2 -1 16 17
+Display: 00 1101 001110 00010010
+Stimuli: -1 0 17 18
+Display: 00 1101 001110 00010010
+Stimuli: 0 1 18 19
+Display: 00 1101 001110 00010010
+Stimuli: 1 2 19 20
+Display: 00 0001 010010 00010010
+Stimuli: -2 3 20 21
+Display: 00 0001 010010 00010010
+Stimuli: -1 4 21 22
+Display: 00 0001 010010 00010010
+Stimuli: 0 5 22 23
+Display: 00 0001 010010 00010010
+Stimuli: 1 6 23 24
+Display: 00 0101 010110 00010010
+Stimuli: -2 7 24 25
+Display: 00 0101 010110 00010010
+Stimuli: -1 -8 25 26
+Display: 00 0101 010110 00010010
+Stimuli: 0 -7 26 27
+Display: 00 0101 010110 00100010
+Stimuli: 1 -6 27 28
+Display: 00 1001 011010 00100010
+Stimuli: -2 -5 28 29
+Display: 00 1001 011010 00100010
+Stimuli: -1 -4 29 30
+Display: 00 1001 011010 00100010
+Stimuli: 0 -3 30 31
+Display: 00 1001 011010 00100010
+Stimuli: 1 -2 31 32
+Display: 00 1101 011110 00100010
+Stimuli: -2 -1 -32 33
+Display: 00 1101 011110 00100010
+Stimuli: -1 0 -31 34
+Display: 00 1101 011110 00100010
+Stimuli: 0 1 -30 35
+Display: 00 1101 011110 00100010
+Stimuli: 1 2 -29 36
+Display: 00 0001 100010 00100010
+Stimuli: -2 3 -28 37
+Display: 00 0001 100010 00100010
+Stimuli: -1 4 -27 38
+Display: 00 0001 100010 00100010
+Stimuli: 0 5 -26 39
+Display: 00 0001 100010 00100010
+Stimuli: 1 6 -25 40
+Display: 00 0101 100110 00100010
+Stimuli: -2 7 -24 41
+Display: 00 0101 100110 00100010
+Stimuli: -1 -8 -23 42
+Display: 00 0101 100110 00100010
+Stimuli: 0 -7 -22 43
+Display: 00 0101 100110 00110010
+Stimuli: 1 -6 -21 44
+Display: 00 1001 101010 00110010
+Stimuli: -2 -5 -20 45
+Display: 00 1001 101010 00110010
+Stimuli: -1 -4 -19 46
+Display: 00 1001 101010 00110010
+Stimuli: 0 -3 -18 47
+Display: 00 1001 101010 00110010
+Stimuli: 1 -2 -17 48
+Display: 00 1101 101110 00110010
+Stimuli: -2 -1 -16 49
+Display: 00 1101 101110 00110010
+Stimuli: -1 0 -15 50
+Display: 00 1101 101110 00110010
+Stimuli: 0 1 -14 51
+Display: 00 1101 101110 00110010
+Stimuli: 1 2 -13 52
+Display: 00 0001 110010 00110010
+Stimuli: -2 3 -12 53
+Display: 00 0001 110010 00110010
+Stimuli: -1 4 -11 54
+Display: 00 0001 110010 00110010
+Stimuli: 0 5 -10 55
+Display: 00 0001 110010 00110010
+Stimuli: 1 6 -9 56
+Display: 00 0101 110110 00110010
+Stimuli: -2 7 -8 57
+Display: 00 0101 110110 00110010
+Stimuli: -1 -8 -7 58
+Display: 00 0101 110110 00110010
+Stimuli: 0 -7 -6 59
+Display: 00 0101 110110 01000010
+Stimuli: 1 -6 -5 60
+Display: 00 1001 111010 01000010
+Stimuli: -2 -5 -4 61
+Display: 00 1001 111010 01000010
+Stimuli: -1 -4 -3 62
+Display: 00 1001 111010 01000010
+Stimuli: 0 -3 -2 63
+Display: 00 1001 111010 01000010
+Stimuli: 1 -2 -1 64
+Display: 00 1101 111110 01000010
+Stimuli: -2 -1 0 65
+Display: 00 1101 111110 01000010
+Stimuli: -1 0 1 66
+Display: 00 1101 111110 01000010
+Stimuli: 0 1 2 67
+Display: 00 1101 111110 01000010
+Stimuli: 1 2 3 68
+Display: 00 0001 000010 01000010
+Stimuli: -2 3 4 69
+Display: 00 0001 000010 01000010
+Stimuli: -1 4 5 70
+Display: 00 0001 000010 01000010
+Stimuli: 0 5 6 71
+Display: 00 0001 000010 01000010
+Stimuli: 1 6 7 72
+Display: 00 0101 000110 01000010
+Stimuli: -2 7 8 73
+Display: 00 0101 000110 01000010
+Stimuli: -1 -8 9 74
+Display: 00 0101 000110 01000010
+Stimuli: 0 -7 10 75
+Display: 00 0101 000110 01010010
+Stimuli: 1 -6 11 76
+Display: 00 1001 001010 01010010
+Stimuli: -2 -5 12 77
+Display: 00 1001 001010 01010010
+Stimuli: -1 -4 13 78
+Display: 00 1001 001010 01010010
+Stimuli: 0 -3 14 79
+Display: 00 1001 001010 01010010
+Stimuli: 1 -2 15 80
+Display: 00 1101 001110 01010010
+Stimuli: -2 -1 16 81
+Display: 00 1101 001110 01010010
+Stimuli: -1 0 17 82
+Display: 00 1101 001110 01010010
+Stimuli: 0 1 18 83
+Display: 00 1101 001110 01010010
+Stimuli: 1 2 19 84
+Display: 00 0001 010010 01010010
+Stimuli: -2 3 20 85
+Display: 00 0001 010010 01010010
+Stimuli: -1 4 21 86
+Display: 00 0001 010010 01010010
+Stimuli: 0 5 22 87
+Display: 00 0001 010010 01010010
+Stimuli: 1 6 23 88
+Display: 00 0101 010110 01010010
+Stimuli: -2 7 24 89
+Display: 00 0101 010110 01010010
+Stimuli: -1 -8 25 90
+Display: 00 0101 010110 01010010
+Stimuli: 0 -7 26 91
+Display: 00 0101 010110 01100010
+Stimuli: 1 -6 27 92
+Display: 00 1001 011010 01100010
+Stimuli: -2 -5 28 93
+Display: 00 1001 011010 01100010
+Stimuli: -1 -4 29 94
+Display: 00 1001 011010 01100010
+Stimuli: 0 -3 30 95
+Display: 00 1001 011010 01100010
+Stimuli: 1 -2 31 96
+Display: 00 1101 011110 01100010
+Stimuli: -2 -1 -32 97
+Display: 00 1101 011110 01100010
+Stimuli: -1 0 -31 98
+Display: 00 1101 011110 01100010
+Stimuli: 0 1 -30 99
+Display: 00 1101 011110 01100010
+Stimuli: 1 2 -29 100
+Display: 00 0001 100010 01100010
+Stimuli: -2 3 -28 101
+Display: 00 0001 100010 01100010
+Stimuli: -1 4 -27 102
+Display: 00 0001 100010 01100010
+Stimuli: 0 5 -26 103
+Display: 00 0001 100010 01100010
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/main.cpp
new file mode 100644
index 000000000..61341a228
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/main.cpp
@@ -0,0 +1,95 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  main.cpp -- 
+
+  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+
+#include "stimulus.h"
+#include "display.h"
+#include "bitwidth.h"
+
+int sc_main (int argc , char *argv[]) {
+  sc_clock        clock;
+  sc_signal<bool> reset;
+  sc_signal_bool_vector2      stimulus_line1;
+  sc_signal_bool_vector4      stimulus_line2;
+  sc_signal_bool_vector6      stimulus_line3;
+  sc_signal_bool_vector8      stimulus_line4;
+  sc_signal<bool>             input_valid;
+  sc_signal<bool>             ack;
+  sc_signal<bool>             output_valid;
+  sc_signal_bool_vector2      result_line1;
+  sc_signal_bool_vector4      result_line2;
+  sc_signal_bool_vector6      result_line3;
+  sc_signal_bool_vector8      result_line4;
+
+  stimulus stimulus1("stimulus_block",
+                      clock,
+		      reset,
+                      stimulus_line1,
+                      stimulus_line2,
+                      stimulus_line3,
+                      stimulus_line4,
+		      input_valid,
+                      ack);
+
+  bitwidth bitwidth1( "process_body",
+                       clock, 
+		       reset,
+                       stimulus_line1,
+                       stimulus_line2,
+                       stimulus_line3,
+                       stimulus_line4,
+		       input_valid,
+                       result_line1, 
+                       result_line2, 
+                       result_line3, 
+                       result_line4,
+                       ack, 
+		       output_valid);
+
+  display  display1( "display_block",
+                       clock,
+		       result_line1,
+		       result_line2,
+		       result_line3,
+		       result_line4,
+		       output_valid);
+
+    sc_start();
+    return 0;
+}
+
+// EOF
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.cpp
new file mode 100644
index 000000000..4ce6064b4
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.cpp
@@ -0,0 +1,73 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  stimulus.cpp -- 
+
+  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+
+#include "stimulus.h"
+
+void stimulus::entry() {
+
+    reset.write(true);
+    wait();
+    reset.write(false);
+
+    sc_signed tmp1(2);
+    sc_signed tmp2(4);
+    sc_signed tmp3(6);
+    sc_signed tmp4(8);
+
+    tmp1 = "0b00";
+    tmp2 = "0b0001";
+    tmp3 = "0b000010";
+    tmp4 = "0b00000011";
+
+    while(true){
+       out_valid.write(true);    
+       out_value1.write(tmp1);
+       out_value2.write(tmp2);
+       out_value3.write(tmp3);
+       out_value4.write(tmp4);
+       cout << "Stimuli: "<< tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << endl;
+       tmp1 = tmp1 + 1;
+       tmp2 = tmp2 + 1;
+       tmp3 = tmp3 + 1;
+       tmp4 = tmp4 + 1;
+       do { wait(); } while (in_ack==false);
+       out_valid.write(false);
+       wait();
+    }
+}
+// EOF
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.h
new file mode 100644
index 000000000..0fa07858c
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.h
@@ -0,0 +1,84 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  stimulus.h -- 
+
+  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+
+#include "common.h"
+
+SC_MODULE( stimulus )
+{
+    SC_HAS_PROCESS( stimulus );
+
+    sc_in_clk clk;
+
+    sc_signal<bool>&             reset ;
+    sc_signal_bool_vector2&      out_value1;     // Output  port
+    sc_signal_bool_vector4&      out_value2;     // Output  port
+    sc_signal_bool_vector6&      out_value3;     // Output  port
+    sc_signal_bool_vector8&      out_value4;     // Output  port
+    sc_signal<bool>&             out_valid;                         // Output  port
+    const sc_signal<bool>&       in_ack;
+
+    //
+    // Constructor
+    //
+
+    stimulus(
+        sc_module_name    NAME,      // reference name
+        sc_clock&      CLK,          // clock
+        sc_signal<bool>& RESET,
+        sc_signal_bool_vector2&            OUT_VALUE1,
+        sc_signal_bool_vector4&            OUT_VALUE2,
+        sc_signal_bool_vector6&            OUT_VALUE3,
+        sc_signal_bool_vector8&            OUT_VALUE4,
+        sc_signal<bool>&                   OUT_VALID,
+        const sc_signal<bool>&             IN_ACK
+        )
+        : 
+          reset        (RESET),
+          out_value1    (OUT_VALUE1),
+          out_value2    (OUT_VALUE2),
+          out_value3    (OUT_VALUE3),
+          out_value4    (OUT_VALUE4),
+          out_valid     (OUT_VALID),
+          in_ack        (IN_ACK) 
+   {
+     clk          (CLK);
+	 SC_CTHREAD( entry, clk.pos() );
+   };
+  void entry();
+};
+// EOF