systemc: Import tests from the Accellera systemc distribution.

Change-Id: Iad76b398949a55d768a34d027a2d8e3739953da6
Reviewed-on: https://gem5-review.googlesource.com/10845
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

15 files changed, 1581 insertions, 0 deletions

diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901.cpp
new file mode 100644
index 000000000..3ed026600
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901.cpp
@@ -0,0 +1,81 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901.cpp -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#include "a2901.h"
+#include "a2901_test.h"
+
+SC_MODULE( twosome )
+{
+    // signals
+    sig4 Y;
+    sig1 t_RAM0, t_RAM3, t_Q0, t_Q3, C4;
+    sig1 Gbar, Pbar, OVR, F3, F30;
+    sig9 I;
+    sig4 Aadd, Badd, D;
+    sig1 RAM0, RAM3, Q0, Q3, C0, OEbar;
+
+    // modules
+    a2901 SLICE;
+    a2901_test TB;
+
+    // constructor
+    twosome( sc_module_name,
+             const sc_clock& CLK_ )
+    : SLICE( "a2901",
+             CLK_,
+             I, Aadd, Badd, D, RAM0, RAM3, Q0, Q3, C0, OEbar,
+             Y, t_RAM0, t_RAM3, t_Q0, t_Q3, C4, Gbar, Pbar, OVR, F3, F30 ),
+      TB( "a2901_test",
+          CLK_,
+          Y, t_RAM0, t_RAM3, t_Q0, t_Q3, C4, Gbar, Pbar, OVR, F3, F30,
+          I, Aadd, Badd, D, RAM0, RAM3, Q0, Q3, C0, OEbar )
+    {}
+};
+
+int
+sc_main( int, char*[] )
+{
+    sc_clock clk;
+
+    twosome AA( "AA", clk );
+
+    sc_start( 410000, SC_NS );
+
+    cout << sc_time_stamp() << endl;
+
+    return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901.f b/src/systemc/tests/systemc/misc/examples/a2901/a2901.f
new file mode 100644
index 000000000..fa477be5e
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901.f
@@ -0,0 +1,6 @@
+a2901/a2901.cpp
+a2901/a2901_alu.cpp
+a2901/a2901_alu_inputs.cpp
+a2901/a2901_edge.cpp
+a2901/a2901_output_and_shifter.cpp
+a2901/a2901_test.cpp
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901.h
new file mode 100644
index 000000000..59c22a29c
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901.h
@@ -0,0 +1,105 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901.h -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#ifndef A2901_H
+#define A2901_H
+
+#include "a2901_alu.h"
+#include "a2901_alu_inputs.h"
+#include "a2901_output_and_shifter.h"
+#include "a2901_edge.h"
+
+SC_MODULE( a2901 )
+{
+    // shared state
+    long RAM[15];
+
+    // signals
+    sig4 RE, S, F, Q, A;
+    sig5 R_ext, S_ext;
+
+    // constructor
+    a2901( sc_module_name,
+           const sc_clock& CLK_,
+           const sig9& I_,
+           const sig4& Aadd_,
+           const sig4& Badd_,
+           const sig4& D_,
+           const sig1& RAM0_,
+           const sig1& RAM3_,
+           const sig1& Q0_,
+           const sig1& Q3_,
+           const sig1& C0_,
+           const sig1& OEbar_,
+           sig4&       Y_,
+           sig1&       t_RAM0_,
+           sig1&       t_RAM3_,
+           sig1&       t_Q0_,
+           sig1&       t_Q3_,
+           sig1&       C4_,
+           sig1&       Gbar_,
+           sig1&       Pbar_,
+           sig1&       OVR_,
+           sig1&       F3_,
+           sig1&       F30_ )
+    {
+        SC_NEW( a2901_alu( "alu",
+                           I_, RE, S, C0_,
+                           R_ext, S_ext, F, OVR_, C4_, Pbar_, Gbar_,
+                           F3_, F30_ ) );
+        SC_NEW( a2901_alu_inputs( "alu_inputs",
+                                  RAM,
+                                  I_, Aadd_, Badd_, D_, Q,
+                                  RE, S, A ) );
+        SC_NEW( a2901_output_and_shifter( "o_and_s",
+                                           I_, OEbar_, A, F, Q,
+                                           Y_, t_RAM0_, t_RAM3_,
+                                           t_Q0_, t_Q3_ ) );
+        SC_NEW( a2901_edge( "edge",
+                            CLK_,
+                            RAM,
+                            I_, Badd_, F, Q3_, Q0_, RAM3_, RAM0_,
+                            Q ) );
+        // initialize the RAM (to get rid of UMRs)
+        for( int i = 0; i < 15; ++ i ) {
+            RAM[0] = 0;
+        }
+    }
+};
+
+#endif
+
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.cpp
new file mode 100644
index 000000000..b8862c63d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.cpp
@@ -0,0 +1,88 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_alu.cpp -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#include "a2901_alu.h"
+
+void
+a2901_alu::entry()
+{
+    int I53 = I.read().range(5,3);
+
+    R_ext_v = (I53 == 0x1) ? sc_int<5> (0xf & ~(RE.read()))
+                           : sc_int<5>( RE.read() );
+    S_ext_v = (I53 == 0x2) ? sc_int<5> (0xf & ~(S.read()) )
+                           : sc_int<5>( S.read() );
+    R_ext.write(R_ext_v);
+    S_ext.write(S_ext_v);
+    
+    switch (I53) {
+    case 0x0:
+    case 0x1:
+    case 0x2:  
+      result = R_ext_v + S_ext_v + C0.read();
+      break;
+    case 0x3:  
+      result = R_ext_v | S_ext_v;
+      break;
+    case 0x4:  
+      result = R_ext_v & S_ext_v;
+      break;
+    case 0x5:  
+      result = ~(R_ext_v) & S_ext_v;
+      break;
+    case 0x6:  
+      result = R_ext_v ^ S_ext_v;
+      break;
+    default:
+      result = ~(R_ext_v ^ S_ext_v);
+    }
+
+    F.write(result);
+    OVR.write(!(R_ext_v[3] ^ S_ext_v[3]) & (R_ext_v[3] ^ result[3]));
+    //C4.write(result[4]);
+    C4.write((bool)result[4]);
+    temp_p = R_ext_v | S_ext_v;
+    temp_g = R_ext_v & S_ext_v;
+    Pbar.write((temp_p[0] & temp_p[1] & temp_p[2] & temp_p[3]) ? 0 : 1);
+    Gbar.write((temp_g[3] |
+	       (temp_p[3] & temp_g[2]) |
+	       (temp_p[3] & temp_p[2] & temp_g[1]) |
+	       (temp_p[3] & temp_p[2] & temp_p[1] & temp_g[0])) ? 0 : 1);
+    //F3.write(result[3]);
+    F3.write((bool)result[3]);
+    F30.write((result[3] | result[2] | result[1] | result[0]) ? 0 : 1);
+}
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.h
new file mode 100644
index 000000000..99bfbfcdd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.h
@@ -0,0 +1,111 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_alu.h -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#ifndef A2901_ALU_H
+#define A2901_ALU_H
+
+#include "common.h"
+
+SC_MODULE( a2901_alu )
+{
+    SC_HAS_PROCESS( a2901_alu );
+
+    // inputs
+    const sig9& I;
+    const sig4& RE;
+    const sig4& S;
+    const sig1& C0;
+
+    // outputs
+    sig5& R_ext;
+    sig5& S_ext;
+    sig4& F;
+    sig1& OVR;
+    sig1& C4;
+    sig1& Pbar;
+    sig1& Gbar;
+    sig1& F3;
+    sig1& F30;
+
+    // temporaries
+    int5 result;
+    int5 R_ext_v;
+    int5 S_ext_v;
+    int5 temp_p;
+    int5 temp_g;
+
+    // constructor
+    a2901_alu( sc_module_name,
+               const sig9& I_,
+               const sig4& RE_,
+               const sig4& S_,
+               const sig1& C0_,
+               sig5&       R_ext_,
+               sig5&       S_ext_,
+               sig4&       F_,
+               sig1&       OVR_,
+               sig1&       C4_,
+               sig1&       Pbar_,
+               sig1&       Gbar_,
+               sig1&       F3_,
+               sig1&       F30_ )
+    : I( I_ ),
+      RE( RE_ ),
+      S( S_ ),
+      C0( C0_ ),
+      R_ext( R_ext_ ),
+      S_ext( S_ext_ ),
+      F( F_ ),
+      OVR( OVR_ ),
+      C4( C4_ ),
+      Pbar( Pbar_ ),
+      Gbar( Gbar_ ),
+      F3( F3_ ),
+      F30( F30_ )
+    {
+        SC_METHOD( entry );
+        sensitive << I;
+        sensitive << RE;
+        sensitive << S;
+        sensitive << C0;
+    }
+
+    void entry();
+};
+
+#endif
+
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.cpp
new file mode 100644
index 000000000..90d37564e
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.cpp
@@ -0,0 +1,79 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_alu_inputs.cpp -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#include "a2901_alu_inputs.h"
+
+void
+a2901_alu_inputs::entry()
+{
+    int4 Av;
+    int4 B;
+
+    Av = RAM[Aadd.read()];
+    B  = RAM[Badd.read()];
+    A.write(Av);
+
+    switch((int)(I.read().range(2,0))) {
+    case 0x0:
+    case 0x1:  
+      RE.write(Av);
+      break;
+    case 0x2:
+    case 0x3:
+    case 0x4:
+      RE.write(0x0);
+      break;
+    default:
+      RE.write(D.read());
+    }
+
+    switch((int)(I.read().range(2,0))) {
+    case 0x4:
+    case 0x5:  
+      S.write(Av);
+      break;
+    case 0x1:
+    case 0x3:
+      S.write(B);
+      break;
+    case 0x7:
+      S.write(0x0);
+      break;
+    default:
+      S.write(Q.read());
+    }
+}
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.h
new file mode 100644
index 000000000..200c98020
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.h
@@ -0,0 +1,95 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_alu_inputs.h -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#ifndef A2901_ALU_INPUTS_H
+#define A2901_ALU_INPUTS_H
+
+#include "common.h"
+
+SC_MODULE( a2901_alu_inputs )
+{
+    SC_HAS_PROCESS( a2901_alu_inputs );
+
+    // shared state
+    long* RAM;
+
+    // inputs
+    const sig9& I;
+    const sig4& Aadd;
+    const sig4& Badd;
+    const sig4& D;
+    const sig4& Q;
+
+    // outputs
+    sig4& RE;
+    sig4& S;
+    sig4& A;
+
+    // constructor
+    a2901_alu_inputs( sc_module_name,
+                      long* RAM_,
+                      const sig9& I_,
+                      const sig4& Aadd_,
+                      const sig4& Badd_,
+                      const sig4& D_,
+                      const sig4& Q_,
+                      sig4&       RE_,
+                      sig4&       S_,
+                      sig4&       A_ )
+    : RAM( RAM_ ),
+      I( I_ ),
+      Aadd( Aadd_ ),
+      Badd( Badd_ ),
+      D( D_ ),
+      Q( Q_ ),
+      RE( RE_ ),
+      S( S_ ),
+      A( A_ )
+    {
+        SC_METHOD( entry );
+        sensitive << I;
+        sensitive << Aadd;
+        sensitive << Badd;
+        sensitive << D;
+        sensitive << Q;
+    }
+
+    void entry();
+};
+
+#endif
+
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.cpp
new file mode 100644
index 000000000..55be5e060
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.cpp
@@ -0,0 +1,81 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_edge.cpp -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#include "a2901_edge.h"
+
+
+void
+a2901_edge::entry()
+{
+    i86 = I.read().range(8,6);
+    i87 = I.read().range(8,7);
+    q31 = Q.read().range(3,1);
+    q20 = Q.read().range(2,0);
+    f31 = F.read().range(3,1);
+
+    switch ((int)i87) {
+    case 0:
+	RAM[Badd.read()] = RAM[Badd.read()];
+	break;
+    case 1:
+	RAM[Badd.read()] = F.read();
+	break;
+    case 2:
+	RAM[Badd.read()] = (RAM3.read(),f31);
+	break;
+    case 3:
+	RAM[Badd.read()] = (f20, RAM0.read());
+	break;
+    }
+      
+#if SUN_HAS_FIXED_THIS_BUG_IN_SC62
+    Q.write( (i86 == 0x0) ? F.read() :
+	     (i86 == 0x4) ? sc_uint<4>((Q3.read(),q31)) :
+	     (i86 == 0x6) ? sc_uint<4>((q20,Q0.read())) :
+	     Q.read());
+#else
+    if( i86 == 0x0 ) {
+        Q.write( F.read() );
+    } else if( i86 == 0x4 ) {
+        Q.write( ( Q3.read(), q31 ) );
+    } else if( i86 == 0x6 ) {
+        Q.write( ( q20, Q0.read() ) );
+    } else {
+        Q.write( Q.read() );
+    }
+#endif
+}
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.h
new file mode 100644
index 000000000..6af666fac
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_edge.h -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#ifndef A2901_EDGE_H
+#define A2901_EDGE_H
+
+#include "common.h"
+
+SC_MODULE( a2901_edge )
+{
+    SC_HAS_PROCESS( a2901_edge );
+
+    // clock
+    const sc_clock& CLK;
+
+    // shared state
+    long* RAM;
+
+    // inputs
+    const sig9& I;
+    const sig4& Badd;
+    const sig4& F;
+    const sig1& Q3;
+    const sig1& Q0;
+    const sig1& RAM3;
+    const sig1& RAM0;
+
+    // outputs
+    sig4& Q;
+
+    // temporaries
+    sc_uint<3> i86;
+    sc_uint<3> i87;
+    sc_uint<3> q31, q20;
+    sc_uint<3> f31, f20;
+
+    // constructor
+    a2901_edge( sc_module_name,
+                const sc_clock& CLK_,
+                long*           RAM_,
+                const sig9&     I_,
+                const sig4&     Badd_,
+                const sig4&     F_,
+                const sig1&     Q3_,
+                const sig1&     Q0_,
+                const sig1&     RAM3_,
+                const sig1&     RAM0_,
+                sig4&           Q_ )
+    : CLK( CLK_ ),
+      RAM( RAM_ ),
+      I( I_ ),
+      Badd( Badd_ ),
+      F( F_ ),
+      Q3( Q3_ ),
+      Q0( Q0_ ),
+      RAM3( RAM3_ ),
+      RAM0( RAM0_ ),
+      Q( Q_ )
+    {
+        SC_METHOD( entry );
+        sensitive << CLK.posedge_event();
+    }
+
+    void entry();
+};
+
+#endif
+
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.cpp
new file mode 100644
index 000000000..92229c4ec
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.cpp
@@ -0,0 +1,64 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_output_and_shifter.cpp -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#include "a2901_output_and_shifter.h"
+
+void
+a2901_output_and_shifter::entry()
+{
+    bool i8, i7, f0, f3, q0, q3;
+    sc_uint<3> i86;
+    int4 z4;
+
+    z4  = 0x0;
+    i86 = I.read().range(8,6);
+    i8  = I.read()[8];
+    i7  = I.read()[7];
+    f0  = F.read()[0];
+    f3  = F.read()[3];
+    q0  = Q.read()[0];
+    q3  = Q.read()[3];
+
+    Y.write( ( ( i86 == 0x2 ) && ( OEbar.read() == 0x0)) ? (uint64)A.read() :
+	     (!( i86 == 0x2 ) && ( OEbar.read() == 0x0)) ? 
+			(uint64)F.read() : (uint64)z4); 
+
+    t_RAM0 .write( (( i8 == 0x1) && ( i7 == 0x0 )) ? f0 : 0x0);             
+    t_RAM3 .write( (( i8 == 0x1) && ( i7 == 0x1 )) ? f3 : 0x0);           
+    t_Q3   .write( (( i8 == 0x1) && ( i7 == 0x1))  ? q3 : 0x0);         
+    t_Q0   .write( (( i8 == 0x1) && ( i7 == 0x0))  ? q0 : 0x0);         
+}
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.h
new file mode 100644
index 000000000..63eb7513a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.h
@@ -0,0 +1,96 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_output_and_shifter.h -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#ifndef A2901_OUTPUT_AND_SHIFTER_H
+#define A2901_OUTPUT_AND_SHIFTER_H
+
+#include "common.h"
+
+SC_MODULE( a2901_output_and_shifter )
+{
+    SC_HAS_PROCESS( a2901_output_and_shifter );
+
+    // inputs
+    const sig9& I;
+    const sig1& OEbar;
+    const sig4& A;
+    const sig4& F;
+    const sig4& Q;
+
+    // outputs
+    sig4& Y;
+    sig1& t_RAM0;
+    sig1& t_RAM3;
+    sig1& t_Q0;
+    sig1& t_Q3;
+
+    // constructor
+    a2901_output_and_shifter( sc_module_name,
+                              const sig9& I_,
+                              const sig1& OEbar_,
+                              const sig4& A_,
+                              const sig4& F_,
+                              const sig4& Q_,
+                              sig4&       Y_,
+                              sig1&       t_RAM0_,
+                              sig1&       t_RAM3_,
+                              sig1&       t_Q0_,
+                              sig1&       t_Q3_ )
+    : I( I_ ),
+      OEbar( OEbar_ ),
+      A( A_ ),
+      F( F_ ),
+      Q( Q_ ),
+      Y( Y_ ),
+      t_RAM0( t_RAM0_ ),
+      t_RAM3( t_RAM3_ ),
+      t_Q0( t_Q0_ ),
+      t_Q3( t_Q3_ )
+    {
+        SC_METHOD( entry );
+        sensitive << I;
+        sensitive << OEbar;
+        sensitive << A;
+        sensitive << F;
+        sensitive << Q;
+    }
+
+    void entry();
+};
+
+#endif
+
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.cpp
new file mode 100644
index 000000000..a2a66287f
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.cpp
@@ -0,0 +1,472 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_test.cpp -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#include "a2901_test.h"
+
+void
+a2901_test::entry()
+{
+      switch (vec_cnt++) {
+      case 0:
+	I.    write(0x7);
+	D.    write(  0);
+	C0.   write(  0);
+	OEbar.write(  0);
+	break;
+      case 1:
+	I.    write(0x46);
+	D.    write(   0);
+	C0.   write(   0);
+	OEbar.write(   0);
+	break;
+      case 2:
+	if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000 (%0d)\n", (int)Y.read());
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1 (%0d)\n", (int)F30.read());
+	
+	I.write(0x7);
+	D.write(0x0);
+	C0.write(0x0);
+	OEbar.write(0x0);
+	
+	break;
+      case 3:
+	I.write(0x46);
+	D.write(0x0);
+	C0.write(0x1);		
+	OEbar.write(0x0);
+	break;
+      case 4:
+	if (Y.read() != 0x1) fprintf(stderr,"Y != 4'b0001\n");
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I.write(0x7);
+	D.write(0xf);					// N("4'b1111")
+	C0.write(0x0);
+	OEbar.write(0x0);
+
+	break;
+      case 5:
+	I.write(0x46);
+	D.write(0x0);
+	C0.write(0x0);
+	OEbar.write(0x0);
+
+	break;
+      case 6:
+	if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n");
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I.write(0x7);
+	D.write(0xf);
+	C0.write(0x0);
+	OEbar.write(0x0);
+
+	break;
+      case 7:
+	I.write(0x46);
+	D.write(0x0);
+	C0.write(0x1);
+	OEbar.write(0x0);
+	break;
+      case 8:
+	if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n");
+	if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n");
+	
+	I.write(0x7);
+	D.write(0xf);
+	C0.write(0x0);
+	OEbar.write(0x0);
+	break;
+      case 9:
+	I.write(0x46);
+	D.write(0xf);
+	C0.write(0x0);
+	OEbar.write(0x0);
+	break;
+      case 10:
+	if (Y.read() != 0xe) fprintf(stderr,"Y != 4'b1110\n");
+	if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n");
+	if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I.write(0x7);
+	D.write(0xf);
+	C0.write(0x0);
+	OEbar.write(0x0);
+	break;
+      case 11:
+	I.write(0x46);
+	D.write(0xf);
+	C0.write(0x1);
+	OEbar.write(0x0);
+	break;
+      case 12:
+	if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n");
+	if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n");
+	if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I .write( 0x7);
+	D .write( 0x0);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 13:
+	I .write( 0x46);
+	D .write( 0xf);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 14:
+	if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n");
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I .write( 0x7);
+	D .write( 0x0);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 15:
+	I .write( 0x46);
+	D .write( 0xf);
+	C0 .write( 0x1);
+	OEbar .write( 0x0);
+	break;
+      case 16:
+	if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n");
+	if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n");
+	
+	I .write( 0x7);
+	D .write( 0x1);				       
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 17:
+	I .write( 0x6);	
+	D .write( 0x1);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 18:
+	if (Y.read() != 0x2) fprintf(stderr,"Y != 4'b0010\n");
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I .write( 0x7);
+	D .write( 0x2);					// N("4'b0010")
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 19:
+	I .write( 0x46);
+	D .write( 0x2);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 20:
+	if (Y.read() != 0x4) fprintf(stderr,"Y != 4'b0100\n");
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I .write( 0x7);
+	D .write( 0x4);					
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	
+	break;
+      case 21:
+	I .write( 0x46);
+	D .write( 0x4);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 22:
+	if (Y.read() != 0x8) fprintf(stderr,"Y != 4'b1000\n");
+	if (C4.read()!= 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n");
+	if (OVR.read() != 0x1) fprintf(stderr,"OVR != 1'b1\n");
+	if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I .write( 0x7);
+	D .write( 0x8);					// N("4'b1000")
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 23:
+	I .write( 0x46);
+	D .write( 0x8);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+
+	break;
+      case 24:
+	if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n");
+	if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n");
+	if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n");
+	if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n");
+	if (OVR.read() != 0x1) fprintf(stderr,"OVR != 1'b1\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n");
+
+	// ******** SUBTRACTION S - R ********
+	I .write( 0x7);
+	D .write( 0x0);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 25:
+	I .write( 0x4e);					// N("9'b001001110")
+	D .write( 0x0);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	
+	break;
+      case 26:
+	if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n");
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+
+	I .write( 0x7);
+	D .write( 0x0);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 27:
+	I .write( 0x4e);
+	D .write( 0x0);
+	C0 .write( 0x1);
+	OEbar .write( 0x0);
+	break;
+      case 28:
+	if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n");
+	if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n");
+
+	I .write( 0x7);
+	D .write( 0x0);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 29:
+	I .write( 0x4e);
+	D .write( 0xf);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);	
+	break;
+      case 30:
+	if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n");
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n");
+	
+	I .write( 0x7);
+	D .write( 0x0);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 31:
+	I .write( 0x4e);
+	D .write( 0xf);
+	C0 .write( 0x1);
+	OEbar .write( 0x0);
+
+	break;
+      case 32:
+	if (Y.read() != 0x1) fprintf(stderr,"Y != 4'b0001\n");
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I .write( 0x7);
+	D .write( 0xf);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	
+	break;
+      case 33:
+	I .write( 0x4e);
+	D .write( 0xf);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	
+	break;
+      case 34:
+	if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n");
+	if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I .write( 0x7);
+	D .write( 0xf);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);	
+	break;
+      case 35:
+	I .write( 0x4e);
+	D .write( 0xf);
+	C0 .write( 0x1);
+	OEbar .write( 0x0);
+	
+	break;
+      case 36:
+	if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n");
+	if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n");
+	if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n");
+	if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n");
+	
+	I .write( 0x7);
+	D .write( 0xf);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+
+	break;
+      case 37:
+	I .write( 0x4e);
+	D .write( 0x0);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+
+	break;
+      case 38:
+	if (Y.read() != 0xe) fprintf(stderr,"Y != 4'b1110\n");
+	if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n");
+	if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+	
+	I .write( 0x7);
+	D .write( 0xf);
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	break;
+      case 39:
+	I .write( 0x4e);
+	D .write( 0x0);
+	C0 .write( 0x1);
+	OEbar .write( 0x0);
+	break;
+      case 40:
+	if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n");
+	if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n");
+	if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n");
+	if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n");
+	if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n");
+	if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n");
+	if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n");
+
+	I .write( 0x7);
+	D .write( 0x0); // 0x1;
+	C0 .write( 0x0);
+	OEbar .write( 0x0);
+	
+	if (++loop < 100000)
+	  vec_cnt = 0;
+	else {
+          printf ("loops = %d\n", loop);
+	  sc_stop();
+        }
+	break;
+      }
+}
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.h
new file mode 100644
index 000000000..e4edd755f
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.h
@@ -0,0 +1,146 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  a2901_test.h -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#ifndef A2901_TEST_H
+#define A2901_TEST_H
+
+#include "common.h"
+
+SC_MODULE( a2901_test )
+{
+    SC_HAS_PROCESS( a2901_test );
+
+    // clock
+    const sc_clock& CLK;
+
+    // inputs
+    const sig4& Y;
+    const sig1& t_RAM0;
+    const sig1& t_RAM3;
+    const sig1& t_Q0;
+    const sig1& t_Q3;
+    const sig1& C4;
+    const sig1& Gbar;
+    const sig1& Pbar;
+    const sig1& OVR;
+    const sig1& F3;
+    const sig1& F30;
+
+    // outputs
+    sig9& I;
+    sig4& Aadd;
+    sig4& Badd;
+    sig4& D;
+    sig1& RAM0;
+    sig1& RAM3;
+    sig1& Q0;
+    sig1& Q3;
+    sig1& C0;
+    sig1& OEbar;
+
+    // temporaries
+    int vec_cnt;
+    int loop;
+
+    // constructor
+    a2901_test( sc_module_name,
+                const sc_clock& CLK_,
+                const sig4& Y_,
+                const sig1& t_RAM0_,
+                const sig1& t_RAM3_,
+                const sig1& t_Q0_,
+                const sig1& t_Q3_,
+                const sig1& C4_,
+                const sig1& Gbar_,
+                const sig1& Pbar_,
+                const sig1& OVR_,
+                const sig1& F3_,
+                const sig1& F30_,
+                sig9&       I_,
+                sig4&       Aadd_,
+                sig4&       Badd_,
+                sig4&       D_,
+                sig1&       RAM0_,
+                sig1&       RAM3_,
+                sig1&       Q0_,
+                sig1&       Q3_,
+                sig1&       C0_,
+                sig1&       OEbar_ )
+    : CLK( CLK_ ),
+      Y( Y_ ),
+      t_RAM0( t_RAM0_ ),
+      t_RAM3( t_RAM3_ ),
+      t_Q0( t_Q0_ ),
+      t_Q3( t_Q3_ ),
+      C4( C4_ ),
+      Gbar( Gbar_ ),
+      Pbar( Pbar_ ),
+      OVR( OVR_ ),
+      F3( F3_ ),
+      F30( F30_ ),
+      I( I_ ),
+      Aadd( Aadd_ ),
+      Badd( Badd_ ),
+      D( D_ ),
+      RAM0( RAM0_ ),
+      RAM3( RAM3_ ),
+      Q0( Q0_ ),
+      Q3( Q3_ ),
+      C0( C0_ ),
+      OEbar( OEbar_ )
+    {
+        vec_cnt = 0;
+        loop = 0;
+
+        // init
+        I.write( 0x7 );
+        D.write( 0 );
+        C0.write( 0 );
+        OEbar.write( 0 );
+        Aadd.write( 0 );
+        Badd.write( 0 );
+        Q0.write( 0 );
+        Q3.write( 0 );
+
+        SC_METHOD( entry );
+        sensitive << CLK.posedge_event();
+    }
+
+    void entry();
+};
+
+#endif
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/common.h b/src/systemc/tests/systemc/misc/examples/a2901/common.h
new file mode 100644
index 000000000..073976081
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/common.h
@@ -0,0 +1,53 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  common.h -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#ifndef COMMON_H
+#define COMMON_H
+
+#include "systemc.h"
+
+typedef bool       int1;
+typedef sc_uint<4> int4;
+typedef sc_uint<5> int5;
+typedef sc_uint<9> int9;
+
+typedef sc_signal<int1> sig1;
+typedef sc_signal<int4> sig4;
+typedef sc_signal<int5> sig5;
+typedef sc_signal<int9> sig9;
+
+#endif
diff --git a/src/systemc/tests/systemc/misc/examples/a2901/golden/a2901.log b/src/systemc/tests/systemc/misc/examples/a2901/golden/a2901.log
new file mode 100644
index 000000000..5667dbd19
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/examples/a2901/golden/a2901.log
@@ -0,0 +1,2 @@
+SystemC Simulation
+410 us