diff options
author | Gabe Black <gabeblack@google.com> | 2018-05-24 01:37:55 -0700 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2018-08-08 10:09:54 +0000 |
commit | 16fa8d7cc8c92f5ab879e4cf9c6c0bbb3567860f (patch) | |
tree | 7b6faaacb4574a555e561534aa4a8508c0624c32 /src/systemc/tests/systemc/misc/stars/star111657 | |
parent | 7235d3b5211d0ba8f528d930a4c1e7ad62eec51a (diff) | |
download | gem5-16fa8d7cc8c92f5ab879e4cf9c6c0bbb3567860f.tar.xz |
systemc: Import tests from the Accellera systemc distribution.
Change-Id: Iad76b398949a55d768a34d027a2d8e3739953da6
Reviewed-on: https://gem5-review.googlesource.com/10845
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/systemc/tests/systemc/misc/stars/star111657')
3 files changed, 475 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/stars/star111657/COMPILE b/src/systemc/tests/systemc/misc/stars/star111657/COMPILE new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/src/systemc/tests/systemc/misc/stars/star111657/COMPILE diff --git a/src/systemc/tests/systemc/misc/stars/star111657/io_controller1.h b/src/systemc/tests/systemc/misc/stars/star111657/io_controller1.h new file mode 100644 index 000000000..5d5f311df --- /dev/null +++ b/src/systemc/tests/systemc/misc/stars/star111657/io_controller1.h @@ -0,0 +1,151 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + io_controller1.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* +############################################################################ +# Siemens AG copyright 2000 +# All Rights Reserved +# +# File name : io_controller.h +# +# Title : I/O-Controller +# +# Purpose : definitions for I/O-Controller-module +# +# Author : Hannes Muhr +# PSE EZE MSA +# +############################################################################## +# Modification History : +# +# +##############################################################################*/ + +#ifndef IO_CONTROLLER_INC +#define IO_CONTROLLER_INC + +#ifdef LOGGING +#include <fstream> +#endif +#include "systemc.h" + + +#ifdef LOGGING +/* stream for logging */ +extern ofstream flog; +#endif + +#define SCAN_INTERVAL 200000 // 200 us +#define NS *1e-9 + +#define MII_FRAME_SIZE 400 + +SC_MODULE(io_controller_m){ + + /* ports */ + sc_in_clk clk_i486_if; + + sc_out<sc_uint<30> > addr30_o1; + sc_out<sc_uint<30> > addr30_o2; + sc_inout<sc_uint<32> > data32_i; + sc_out<sc_uint<32> > data32_o1; + sc_out<sc_uint<32> > data32_o2; + sc_out<bool> ads_n_o1; + sc_out<bool> ads_n_o2; + sc_out<bool> wr_n_o1; + sc_out<bool> wr_n_o2; + sc_in<bool> rdy_n_i; + sc_in<bool> ar_i; + sc_in<bool> res_n_i; + + sc_out<sc_uint<4> > mii_data4_o; + sc_out<bool> mii_en_o; + sc_in<sc_uint<4> > mii_data4_i; + sc_in<bool> mii_en_i; + sc_in<bool> mii_coll_det; + sc_in_clk clk_mii; + + /* signals */ + sc_signal<bool> start_mux; + sc_signal<bool> ready_mux; + sc_signal<bool> start_read; + sc_signal<bool> out_fifo_reset; + + /* variables */ + sc_uint<32> addr_tx_frame_ptr; + sc_uint<32> rx_ptr_array; + sc_signal<bool> sem1; // mutual exclusion for i486-if + sc_signal<bool> sem2; // mutual exclusion for i486-if + sc_uint<32> shared_mem1[MII_FRAME_SIZE]; // for write + sc_uint<32> shared_mem2[MII_FRAME_SIZE]; // for read + + SC_CTOR(io_controller_m){ + + SC_CTHREAD(control_write, clk_i486_if.pos()); + //reset_signal_is(mii_coll_det, true); + reset_signal_is(res_n_i, false); + + SC_CTHREAD(control_read, clk_i486_if.pos()); + + SC_CTHREAD(mux, clk_mii.pos()); + SC_CTHREAD(shift, clk_mii.pos()); + + + /* Initialize */ + start_mux = 0; + ready_mux = 0; + start_read = 0; + out_fifo_reset = 0; + + sem1 = false; + sem2 = false; + // init shared memory + for (int i=0; i < MII_FRAME_SIZE; i++) + shared_mem1[i] = shared_mem2[i] = 0; + } + void control_write(); + void control_read(); + void mux(); + void shift(); + sc_uint<32> read_from_memory0(sc_uint<32>); + sc_uint<32> read_from_memory1(sc_uint<32>); + void write_into_memory0(sc_uint<32>, sc_uint<32>); + void write_into_memory1(sc_uint<32>, sc_uint<32>); + +}; + +#endif diff --git a/src/systemc/tests/systemc/misc/stars/star111657/star111657.cpp b/src/systemc/tests/systemc/misc/stars/star111657/star111657.cpp new file mode 100644 index 000000000..5bcbaa724 --- /dev/null +++ b/src/systemc/tests/systemc/misc/stars/star111657/star111657.cpp @@ -0,0 +1,324 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + star111657.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/*############################################################################ +# Siemens AG copyright 2000 +# All Rights Reserved +# +# File name : io_controller.cpp +# +# Title : I/O-Controller +# +# Purpose : functionality for I/O-Controller-module +# +# Author : Hannes Muhr +# PSE EZE MSA +# +############################################################################## +# Modification History : +# +# +##############################################################################*/ + +#include "systemc.h" +#include "io_controller1.h" + + +void io_controller_m::mux(){ + + sc_uint<32> data; + + while (true){ + while (start_mux.read() == 0) wait(); + #ifdef LOGGING + flog << sc_time_stamp()<<": "<<name()<<"::select - enabled" << endl; + #endif + mii_en_o = 1; + for (int i = 0; i < MII_FRAME_SIZE; i++){ + data = shared_mem1[i]; + + mii_data4_o = data.range(3,0); + wait(); + mii_data4_o = data.range(7,4); + wait(); + mii_data4_o = data.range(11,8); + wait(); + mii_data4_o = data.range(15,12); + wait(); + mii_data4_o = data.range(19,16); + wait(); + mii_data4_o = data.range(23,20); + wait(); + mii_data4_o = data.range(27,24); + wait(); + mii_data4_o = data.range(31,28); + wait(); + } + mii_en_o = 0; + mii_data4_o = 0; + ready_mux = 1; + wait(); + ready_mux = 0; + wait(); + } +} + +void io_controller_m::shift(){ + + sc_uint<32> data; + + while (true){ + while (mii_en_i.read() == false) wait(); + #ifdef LOGGING + flog << sc_time_stamp()<<": "<<name()<<"::collect - enabled" << endl; + #endif + + for (int i = 0; i < MII_FRAME_SIZE; i++){ + data.range(3,0) = mii_data4_i; + wait(); + data.range(7,4) = mii_data4_i; + wait(); + data.range(11,8) = mii_data4_i; + wait(); + data.range(15,12) = mii_data4_i; + wait(); + data.range(19,16) = mii_data4_i; + wait(); + data.range(23,20) = mii_data4_i; + wait(); + data.range(27,24) = mii_data4_i; + wait(); + data.range(31,28) = mii_data4_i; + shared_mem2[i] = data; + wait(); + } + start_read = 1; + wait(); + start_read = 0; + wait(); + } +} + +sc_uint<32> io_controller_m::read_from_memory0(sc_uint<32> mp){ + + // read from mbdatm-memory over i486-IF + + addr30_o1 = mp >> 2; + ads_n_o1 = 0; + wr_n_o1 = 0; + wait(); + ads_n_o1 = 1; + while (rdy_n_i.read() == 1) wait(); + sc_uint<32> data = data32_i.read(); + wr_n_o1 = 1; + addr30_o1 = 0; + return data; +} + +sc_uint<32> io_controller_m::read_from_memory1(sc_uint<32> mp){ + + // read from mbdatm-memory over i486-IF + + addr30_o2 = mp >> 2; + ads_n_o2 = 0; + wr_n_o2 = 0; + wait(); + ads_n_o2 = 1; + while (rdy_n_i.read() == 1) wait(); + sc_uint<32> data = data32_i.read(); + wr_n_o2 = 1; + addr30_o2 = 0; + return data; +} + +void io_controller_m::write_into_memory0(sc_uint<32> mp, sc_uint<32> data){ + + addr30_o1 = mp >> 2; + ads_n_o1 = 0; + wr_n_o1 = 1; + wait(); + ads_n_o1 = 1; + data32_o1 = data; + while (rdy_n_i.read() == 1) wait(); + wr_n_o1 = 1; + addr30_o1 = 0; + data32_o1 = 0; +} + +void io_controller_m::write_into_memory1(sc_uint<32> mp, sc_uint<32> data){ + + addr30_o2 = mp >> 2; + ads_n_o2 = 0; + wr_n_o2 = 1; + wait(); + ads_n_o2 = 1; + data32_o2 = data; + while (rdy_n_i.read() == 1) wait(); + wr_n_o2 = 1; + addr30_o2 = 0; + data32_o2 = 0; +} + +void io_controller_m::control_write(){ + sc_uint<32> word_cnt; + + while (res_n_i.read() == 0) wait(); + + // initialize + + // wait for 1. AR (HWS-Daten) + while (ar_i.read() == 0) wait(); + sc_uint<32> hws = data32_i.read(); + + wait(); + + // wait for 2. AR (ACB-Pointer) + while (ar_i.read() == 0) wait(); + addr_tx_frame_ptr = data32_i.read(); + wait(); + + + while(true){ + // normally Attention Request - Signal from MBDATM + // would wake up IO-Controller to read data from the memory, + // but the model from Hr. Wahl said: wait for some ms !!! + + wait(1000); + + #ifdef LOGGING + flog << sc_time_stamp()<<": "<<name()<<"::control_write - Attention Request" << endl; + #endif + + while (sem2) wait(); sem2 = true; // P-operation + sc_uint<32> tx_frame_ptr = read_from_memory0(addr_tx_frame_ptr); + if (tx_frame_ptr != 0) + word_cnt = read_from_memory0(tx_frame_ptr+(MII_FRAME_SIZE+1)*4); + sem2 = false; // V-operation + + // check, if frame available and frame is full (word_cnt == MII_FRAME_SIZE) + + while (tx_frame_ptr != 0 && word_cnt == MII_FRAME_SIZE){ + #ifdef LOGGING + flog << sc_time_stamp()<<": "<<name()<<"::control_write - writing mii_frame into out_fifo" << endl; + #endif + + + for (int i = 0; i<MII_FRAME_SIZE; i++){ + // reading from i486-IF and writing into + // out_fifo is mixed, so read_from_memory could not be applied + + while (sem2) wait(); sem2 = true; // P-operation + sc_uint<32> data = read_from_memory0(tx_frame_ptr+i*4); + sem2 = false; // V-operation + + if (i == 0){ + start_mux = 1; + shared_mem1[i] = data; + wait(); + start_mux = 0; + } + else { + shared_mem1[i] = data; + wait(); + } + // wait(); ?? + } + + while (ready_mux.read() == 0) wait(); + + // write 0xFFFFFFFF (>MII_FRAME_SIZE) into tx_frame_ptr + // to signal software in mbdatm that io-controller has + // read out the frames and sent successfully + while (sem2) wait(); sem2 = true; // P-operation + write_into_memory0(tx_frame_ptr+(MII_FRAME_SIZE+1)*4, 0xFFFFFFFF); + sem2 = false; // V-operation + + // read next frame_pointer and word_cnt from MBDATM + while (sem2) wait(); sem2 = true; // P-operation + tx_frame_ptr = read_from_memory0(tx_frame_ptr+MII_FRAME_SIZE*4); + if (tx_frame_ptr != 0) + word_cnt = read_from_memory0(tx_frame_ptr+(MII_FRAME_SIZE+1)*4); + sem2 = false; // V-operation + + + } + + } +} + +void io_controller_m::control_read(){ + + int arr_ptr = 0; + + while (true){ + while (start_read.read() == 0) wait(); + #ifdef LOGGING + flog << sc_time_stamp()<<": "<<name()<<"::control_read " << endl; + #endif + + // read rx_frame_ptr from MBDATM + while (sem1) wait(); sem1 = true; // P-operation + sc_uint<32> rx_frame_ptr = read_from_memory1(rx_ptr_array+arr_ptr*4); + sem1 = false; // V-operation + /*if (rx_frame_ptr == 0){ + cerr << "\nIO-Controller has read NULL-ptr from rx_array in MBDATM\n"; + cerr << "MBDATM did not fill rx_array fast enough\n"; + exit(-1); + }*/ + if (++arr_ptr == MII_FRAME_SIZE) + arr_ptr = 0; + + // write data from in_fifo into MBDATM-memory + for (int i = 0; i < MII_FRAME_SIZE; i++){ + sc_uint<32> d = shared_mem2[i]; + // grab the semaphore + while (sem1) wait(); sem1 = true; // P-operation + write_into_memory1(rx_frame_ptr + i*4, d); + // release semaphore + sem1 = false; // V-operation + wait(); + + } + + // write 0xFFFFFFFF into word_cnt from frame + // to indicate the software (MBDATM) that frame has been filled + while (sem1) wait(); sem1 = true; // P-operation + write_into_memory1(rx_frame_ptr + (MII_FRAME_SIZE+1)*4, 0xFFFFFFFF); + sem1 = false; // V-operation + } +} + |