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authorGabe Black <gabeblack@google.com>2018-05-24 01:37:55 -0700
committerGabe Black <gabeblack@google.com>2018-08-08 10:09:54 +0000
commit16fa8d7cc8c92f5ab879e4cf9c6c0bbb3567860f (patch)
tree7b6faaacb4574a555e561534aa4a8508c0624c32 /src/systemc/tests/systemc/misc/synth/concat
parent7235d3b5211d0ba8f528d930a4c1e7ad62eec51a (diff)
downloadgem5-16fa8d7cc8c92f5ab879e4cf9c6c0bbb3567860f.tar.xz
systemc: Import tests from the Accellera systemc distribution.
Change-Id: Iad76b398949a55d768a34d027a2d8e3739953da6 Reviewed-on: https://gem5-review.googlesource.com/10845 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/systemc/tests/systemc/misc/synth/concat')
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/define.h55
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/golden/test.log5
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/main.cpp80
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.cpp56
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/tb.cpp52
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/tb.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/test.cpp134
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/test.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/fncall/test.h102
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/define.h55
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/golden/test.log5
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/main.cpp80
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.cpp56
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.cpp52
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/test.cpp131
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/test.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/lvalue/test.h102
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/define.h55
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/golden/test.log5
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/main.cpp80
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.cpp56
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.cpp52
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/test.cpp160
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/test.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/concat/rvalue/test.h102
30 files changed, 2093 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/define.h b/src/systemc/tests/systemc/misc/synth/concat/fncall/define.h
new file mode 100644
index 000000000..d671993cd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/define.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ define.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#define CLOCK_PERIOD 100
+#define TB_CLOCK_PERIOD 50
+#define DUTY_CYCLE 0.5
+#define EVENT_TIME 50
+#define TEST_TIME 50
+
+#define long_wait wait(10)
+#define single_cycle wait(2)
+#define set_value(var,val) wait(); var = val; wait()
+#define test_value(actual, expected) \
+ wait (); if (expected != actual) \
+ cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl; \
+ wait ()
+#define test_value_now(actual, expected) \
+ if (expected != actual) cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl;
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/golden/test.log b/src/systemc/tests/systemc/misc/synth/concat/fncall/golden/test.log
new file mode 100644
index 000000000..510bd7f39
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/golden/test.log
@@ -0,0 +1,5 @@
+SystemC Simulation
+Begin Simulation
+End Simulation
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/main.cpp b/src/systemc/tests/systemc/misc/synth/concat/fncall/main.cpp
new file mode 100644
index 000000000..852905b57
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/main.cpp
@@ -0,0 +1,80 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+// Main routine
+
+#include "systemc.h"
+#include "test.h"
+#include "tb.h"
+#include "monitor.h"
+#include "define.h"
+
+int sc_main(int ac, char *av[])
+{
+ sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
+
+ sc_signal<bool> reset_sig;
+
+ sc_signal<int> i1;
+ sc_signal<int> i2;
+ sc_signal<int> i3;
+ sc_signal<int> i4;
+ sc_signal<int> i5;
+
+ sc_signal<bool> cont1;
+ sc_signal<bool> cont2;
+ sc_signal<bool> cont3;
+
+ sc_signal<int> o1;
+ sc_signal<int> o2;
+ sc_signal<int> o3;
+ sc_signal<int> o4;
+ sc_signal<int> o5;
+
+ test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+
+ // Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.cpp b/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.cpp
new file mode 100644
index 000000000..103437eee
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.cpp
@@ -0,0 +1,56 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "monitor.h"
+
+void monitor::entry()
+{
+ int cycleNo = 0;
+
+ while (true) {
+ cout << "[Cycle No: " << cycleNo << "]" <<
+ " i1 = " << i1 <<
+ " o1 = " << o1 <<
+ " o2 = " << o2 <<
+ " cont1 = " << cont1 <<
+ endl;
+ cycleNo++;
+ wait();
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.h b/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.h
new file mode 100644
index 000000000..a827f7c8a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for monitor process
+ Author: PRP
+ */
+
+SC_MODULE( monitor )
+{
+ SC_HAS_PROCESS( monitor );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ monitor (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.cpp b/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.cpp
new file mode 100644
index 000000000..dfc57d75a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "tb.h"
+#include "define.h"
+
+void tb::entry()
+{
+ cout << "Begin Simulation" << endl;
+
+
+ cout << "End Simulation" << endl;
+
+ sc_stop();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.h b/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.h
new file mode 100644
index 000000000..5e76fb35d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test bench
+ Author: PRP
+ */
+
+SC_MODULE( tb )
+{
+ SC_HAS_PROCESS( tb );
+
+ sc_in_clk clk;
+
+ // Output Reset Port
+ sc_signal<bool>& reset_sig;
+
+ // Output Data Ports
+ sc_signal<int>& i1;
+ sc_signal<int>& i2;
+ sc_signal<int>& i3;
+ sc_signal<int>& i4;
+ sc_signal<int>& i5;
+
+ // Output Control Ports
+ sc_signal<bool>& cont1;
+ sc_signal<bool>& cont2;
+ sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ tb (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ sc_signal<bool>& RESET_SIG,
+
+ sc_signal<int>& I1,
+ sc_signal<int>& I2,
+ sc_signal<int>& I3,
+ sc_signal<int>& I4,
+ sc_signal<int>& I5,
+
+ sc_signal<bool>& CONT1,
+ sc_signal<bool>& CONT2,
+ sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/test.cpp b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.cpp
new file mode 100644
index 000000000..1cb0672fc
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.cpp
@@ -0,0 +1,134 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+//
+// Verifies the functionality of concanetation operation.
+// Operands are arguments to a function
+//
+// Author: PRP
+// Date Created: 19 Feb 99
+//
+
+
+#include "systemc.h"
+#include "test.h"
+
+sc_lv_base AND_fn (const sc_lv_base &a, const sc_lv_base &b)
+{
+ return a | b;
+}
+
+sc_lv_base OR_fn (const sc_lv_base &a, const sc_lv_base &b)
+{
+ return a & b;
+}
+
+void test::entry()
+{
+ sc_lv<8> a;
+ sc_lv<8> b;
+ sc_lv<8> c;
+ sc_lv<8> d;
+ sc_lv<24> e;
+ sc_lv<24> f;
+
+ sc_logic k;
+ sc_logic n;
+ sc_logic m, o, p, q, r, s, t, u;
+
+ sc_lv<32> x;
+ sc_lv<32> y;
+ sc_lv<32> z;
+ sc_lv<32> z1;
+
+
+ while (true) {
+
+ wait ();
+
+ a = "00000000"; // 0
+ b = "00000001"; // 1
+ c = "00000011"; // 3
+ d = "00001111"; // 15
+ e = "000000000000000000000001"; // 1
+ f = "000000000000000000001010"; // 10
+
+ // =============== Array + Array ====================================
+ // variable + variable, cascading
+ x = OR_fn ((a, b, c, d), (d, c, b, a));
+ // x = 00001111 00000011 00000011 00001111
+
+ // variable + constant, cascading, composition
+ y = AND_fn (((a, b, c), "00000000"), (d, "00000000", b, a));
+ // y = 00000000 00000000 00000001 00000000
+
+ // constant + constant
+ z = OR_fn (( sc_lv_base( "0000000000000000" ), "1000000000000000"), x);
+ // z = 00001111 00000011 10000011 00001111
+
+ z = z & (~y);
+ // z = 00001111 00000011 10000010 00001111
+
+ // =============== Array (variable) + Scalar ==============================
+
+ n = '1';
+ o = '0';
+ z = OR_fn (z, ( sc_lv_base( n ), "000000000000000", "0000000000000000"));
+ // z = 10001111 00000011 10000010 00001111
+
+ z = OR_fn (z, ( sc_lv_base( "00000000" ), o, n, d, "00000000000000"));
+ // z = 10001111 01000011 11000010 00001111
+
+ k = '1';
+ z = OR_fn (z, ( sc_lv_base( "00000000" ), "00", k, "00000", "0000000000000000"));
+ // z = 10001111 01100011 11000010 00001111
+
+ // =============== Null Vector ====================================
+
+ z = AND_fn (z, (( sc_lv_base( o ), sc_lv_base( k ), "111111"), "111111111111111111111111"));
+ // z = 00001111 01100011 11000010 00001111
+
+ // =============== LHS/RHS of different widths ==============================
+
+ z1 = OR_fn (z, sc_lv_base( "00000000000000000000000000000000" )); // length of string = 32
+
+ o1 = z.to_int(); // o1 = 00001111 01100011 11000010 00001111
+ wait();
+
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/test.f b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.f
new file mode 100644
index 000000000..050983dc0
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.f
@@ -0,0 +1,4 @@
+fncall/test.cpp
+fncall/tb.cpp
+fncall/monitor.cpp
+fncall/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/test.h b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.h
new file mode 100644
index 000000000..5596f1f8d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( test )
+{
+ SC_HAS_PROCESS( test );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Output Data Ports
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ test (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/define.h b/src/systemc/tests/systemc/misc/synth/concat/lvalue/define.h
new file mode 100644
index 000000000..d671993cd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/define.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ define.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#define CLOCK_PERIOD 100
+#define TB_CLOCK_PERIOD 50
+#define DUTY_CYCLE 0.5
+#define EVENT_TIME 50
+#define TEST_TIME 50
+
+#define long_wait wait(10)
+#define single_cycle wait(2)
+#define set_value(var,val) wait(); var = val; wait()
+#define test_value(actual, expected) \
+ wait (); if (expected != actual) \
+ cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl; \
+ wait ()
+#define test_value_now(actual, expected) \
+ if (expected != actual) cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl;
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/golden/test.log b/src/systemc/tests/systemc/misc/synth/concat/lvalue/golden/test.log
new file mode 100644
index 000000000..510bd7f39
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/golden/test.log
@@ -0,0 +1,5 @@
+SystemC Simulation
+Begin Simulation
+End Simulation
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/main.cpp b/src/systemc/tests/systemc/misc/synth/concat/lvalue/main.cpp
new file mode 100644
index 000000000..852905b57
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/main.cpp
@@ -0,0 +1,80 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+// Main routine
+
+#include "systemc.h"
+#include "test.h"
+#include "tb.h"
+#include "monitor.h"
+#include "define.h"
+
+int sc_main(int ac, char *av[])
+{
+ sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
+
+ sc_signal<bool> reset_sig;
+
+ sc_signal<int> i1;
+ sc_signal<int> i2;
+ sc_signal<int> i3;
+ sc_signal<int> i4;
+ sc_signal<int> i5;
+
+ sc_signal<bool> cont1;
+ sc_signal<bool> cont2;
+ sc_signal<bool> cont3;
+
+ sc_signal<int> o1;
+ sc_signal<int> o2;
+ sc_signal<int> o3;
+ sc_signal<int> o4;
+ sc_signal<int> o5;
+
+ test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+
+ // Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.cpp b/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.cpp
new file mode 100644
index 000000000..103437eee
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.cpp
@@ -0,0 +1,56 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "monitor.h"
+
+void monitor::entry()
+{
+ int cycleNo = 0;
+
+ while (true) {
+ cout << "[Cycle No: " << cycleNo << "]" <<
+ " i1 = " << i1 <<
+ " o1 = " << o1 <<
+ " o2 = " << o2 <<
+ " cont1 = " << cont1 <<
+ endl;
+ cycleNo++;
+ wait();
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.h b/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.h
new file mode 100644
index 000000000..a827f7c8a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for monitor process
+ Author: PRP
+ */
+
+SC_MODULE( monitor )
+{
+ SC_HAS_PROCESS( monitor );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ monitor (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.cpp b/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.cpp
new file mode 100644
index 000000000..dfc57d75a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "tb.h"
+#include "define.h"
+
+void tb::entry()
+{
+ cout << "Begin Simulation" << endl;
+
+
+ cout << "End Simulation" << endl;
+
+ sc_stop();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.h b/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.h
new file mode 100644
index 000000000..5e76fb35d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test bench
+ Author: PRP
+ */
+
+SC_MODULE( tb )
+{
+ SC_HAS_PROCESS( tb );
+
+ sc_in_clk clk;
+
+ // Output Reset Port
+ sc_signal<bool>& reset_sig;
+
+ // Output Data Ports
+ sc_signal<int>& i1;
+ sc_signal<int>& i2;
+ sc_signal<int>& i3;
+ sc_signal<int>& i4;
+ sc_signal<int>& i5;
+
+ // Output Control Ports
+ sc_signal<bool>& cont1;
+ sc_signal<bool>& cont2;
+ sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ tb (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ sc_signal<bool>& RESET_SIG,
+
+ sc_signal<int>& I1,
+ sc_signal<int>& I2,
+ sc_signal<int>& I3,
+ sc_signal<int>& I4,
+ sc_signal<int>& I5,
+
+ sc_signal<bool>& CONT1,
+ sc_signal<bool>& CONT2,
+ sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.cpp b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.cpp
new file mode 100644
index 000000000..e20874af6
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.cpp
@@ -0,0 +1,131 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+//
+// Verifies the functionality of concanetation operation.
+// Operands form the rvalue of an assignment
+//
+// Author: PRP
+// Date Created: 19 Feb 99
+//
+
+
+#include "systemc.h"
+#include "test.h"
+
+void test::entry()
+{
+ sc_lv<8> a;
+ sc_lv<8> b;
+ sc_lv<8> c;
+ sc_lv<8> d;
+ sc_lv<24> e;
+ sc_lv<24> f;
+
+ // sc_logic k;
+ // sc_logic n;
+ // sc_logic m, o, p, q, r, s, t, u;
+ sc_lv<1> k, n, m, o, p, q, r, s, t, u;
+
+ sc_lv<32> x;
+ sc_lv<32> y;
+ sc_lv<32> z;
+
+ int i,j;
+
+ while (true) {
+
+ wait ();
+
+
+ b = "00000001"; // 1
+ c = "00000011"; // 3
+ d = "00001111"; // 15
+
+ // =============== Array + Array ====================================
+
+ (a, f) = "00000000000000000000000000000011"; // a = 0, f = 3
+
+ // =============== Cascading ====================================
+ // cascading array variables
+ (a, f) = (b, c, d, a);
+ // a = 00000001 f = "00000011 00001111 00000000"
+ z = (a, f);
+
+ // composing cascaded array variables
+ x = ( sc_lv_base( "00000011" ), "00000011", "00000011", "00000101");
+ (a, (b, c, d)) = x;
+ z = z | x; // z = 00000011 00000011 00001111 00000101
+
+ // =============== Array (variable) + Scalar ==============================
+
+ (b, c, d, a.range (7, 2), k, n) = (a, b, c, d);
+ // b = 00000011 c = 00000011 d = 00000011 a = 00000111
+ // k = 0 n = 1
+ z = z | (a, b, c, d); // z = 00000111 00000011 00001111 00000111
+
+ ( k, m, a.range (5, 0)) = z.range (15, 8);
+ // k = 0 m = 0 a = 00001111
+ z = z | ( sc_lv_base( n ), m, k, n, "0000", a, "0000000000000000");
+ // z = 10010111 00001111 00001111 00000111
+
+ // =============== Null Vector ====================================
+
+ ( m, n, o, p, q, r, s, t ) = "11011010";
+ a = ( sc_lv_base( s ), t, q, r, o, m, n, p); // a = "10100111"
+ z = (z.range (31, 8), a); // z = 10010111 00001111 00001111 10100111
+
+ b = "00000000";
+
+ z = z | (b, b, b, z.range (7, 0));
+
+ // =============== LHS/RHS of different widths ==============================
+
+ (x.range (15, 0), x.range (31, 16)) = ("1001011100001111000011111010011101");
+ // RHS is (z, "01")
+ // x = 00111110 10011101 01011100 00111100
+
+ (z.range (31, 16), z.range (15, 0)) = (x.range (7, 0), x.range (23, 16),
+ x.range (15, 8), x.range (31, 24));
+ // z = 00111100 10011101 01011100 00111110
+
+ o1 = z.to_int();
+ wait();
+
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.f b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.f
new file mode 100644
index 000000000..5fccdcdd7
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.f
@@ -0,0 +1,4 @@
+lvalue/test.cpp
+lvalue/tb.cpp
+lvalue/monitor.cpp
+lvalue/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.h b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.h
new file mode 100644
index 000000000..5596f1f8d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( test )
+{
+ SC_HAS_PROCESS( test );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Output Data Ports
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ test (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/define.h b/src/systemc/tests/systemc/misc/synth/concat/rvalue/define.h
new file mode 100644
index 000000000..d671993cd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/define.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ define.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#define CLOCK_PERIOD 100
+#define TB_CLOCK_PERIOD 50
+#define DUTY_CYCLE 0.5
+#define EVENT_TIME 50
+#define TEST_TIME 50
+
+#define long_wait wait(10)
+#define single_cycle wait(2)
+#define set_value(var,val) wait(); var = val; wait()
+#define test_value(actual, expected) \
+ wait (); if (expected != actual) \
+ cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl; \
+ wait ()
+#define test_value_now(actual, expected) \
+ if (expected != actual) cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl;
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/golden/test.log b/src/systemc/tests/systemc/misc/synth/concat/rvalue/golden/test.log
new file mode 100644
index 000000000..510bd7f39
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/golden/test.log
@@ -0,0 +1,5 @@
+SystemC Simulation
+Begin Simulation
+End Simulation
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/main.cpp b/src/systemc/tests/systemc/misc/synth/concat/rvalue/main.cpp
new file mode 100644
index 000000000..852905b57
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/main.cpp
@@ -0,0 +1,80 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+// Main routine
+
+#include "systemc.h"
+#include "test.h"
+#include "tb.h"
+#include "monitor.h"
+#include "define.h"
+
+int sc_main(int ac, char *av[])
+{
+ sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
+
+ sc_signal<bool> reset_sig;
+
+ sc_signal<int> i1;
+ sc_signal<int> i2;
+ sc_signal<int> i3;
+ sc_signal<int> i4;
+ sc_signal<int> i5;
+
+ sc_signal<bool> cont1;
+ sc_signal<bool> cont2;
+ sc_signal<bool> cont3;
+
+ sc_signal<int> o1;
+ sc_signal<int> o2;
+ sc_signal<int> o3;
+ sc_signal<int> o4;
+ sc_signal<int> o5;
+
+ test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+
+ // Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.cpp b/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.cpp
new file mode 100644
index 000000000..103437eee
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.cpp
@@ -0,0 +1,56 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "monitor.h"
+
+void monitor::entry()
+{
+ int cycleNo = 0;
+
+ while (true) {
+ cout << "[Cycle No: " << cycleNo << "]" <<
+ " i1 = " << i1 <<
+ " o1 = " << o1 <<
+ " o2 = " << o2 <<
+ " cont1 = " << cont1 <<
+ endl;
+ cycleNo++;
+ wait();
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.h b/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.h
new file mode 100644
index 000000000..a827f7c8a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for monitor process
+ Author: PRP
+ */
+
+SC_MODULE( monitor )
+{
+ SC_HAS_PROCESS( monitor );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ monitor (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.cpp b/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.cpp
new file mode 100644
index 000000000..dfc57d75a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "tb.h"
+#include "define.h"
+
+void tb::entry()
+{
+ cout << "Begin Simulation" << endl;
+
+
+ cout << "End Simulation" << endl;
+
+ sc_stop();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.h b/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.h
new file mode 100644
index 000000000..5e76fb35d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test bench
+ Author: PRP
+ */
+
+SC_MODULE( tb )
+{
+ SC_HAS_PROCESS( tb );
+
+ sc_in_clk clk;
+
+ // Output Reset Port
+ sc_signal<bool>& reset_sig;
+
+ // Output Data Ports
+ sc_signal<int>& i1;
+ sc_signal<int>& i2;
+ sc_signal<int>& i3;
+ sc_signal<int>& i4;
+ sc_signal<int>& i5;
+
+ // Output Control Ports
+ sc_signal<bool>& cont1;
+ sc_signal<bool>& cont2;
+ sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ tb (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ sc_signal<bool>& RESET_SIG,
+
+ sc_signal<int>& I1,
+ sc_signal<int>& I2,
+ sc_signal<int>& I3,
+ sc_signal<int>& I4,
+ sc_signal<int>& I5,
+
+ sc_signal<bool>& CONT1,
+ sc_signal<bool>& CONT2,
+ sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.cpp b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.cpp
new file mode 100644
index 000000000..3a1c86093
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.cpp
@@ -0,0 +1,160 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+//
+// Verifies the functionality of concanetation operation.
+// Operands form the rvalue of an assignment
+//
+// Author: PRP
+// Date Created: 19 Feb 99
+//
+
+
+#include "systemc.h"
+#include "test.h"
+
+void test::entry()
+{
+ sc_lv<8> a;
+ sc_lv<8> b;
+ sc_lv<8> c;
+ sc_lv<8> d;
+ sc_lv<24> e;
+ sc_lv<24> f;
+
+ sc_logic k;
+ sc_logic n;
+ sc_logic m;
+
+ sc_lv<32> x;
+ sc_lv<32> y;
+ sc_lv<32> z;
+
+ sc_lv<2> kk;
+
+ int i,j;
+
+ while (true) {
+
+ wait ();
+
+ // ------- rvalue ---------------------------------------------
+
+ a = "00000000"; // 0
+ b = "00000001"; // 1
+ c = "00000011"; // 3
+ d = "00001111"; // 15
+ e = "000000000000000000000001"; // 1
+ f = "000000000000000000001010"; // 10
+
+ // =============== Array + Array ====================================
+ // array constant + array constant
+ x = ( sc_lv_base( "000000000000000000000000" ), "00010000"); // x = 32
+
+ // array constant + array variable
+ y = ("000000000000000000000000", b); // y = 1
+ z = x | y; // z = 00000000 00000000 00000000 00010001
+
+ // array variable + array constant
+ x = (a, "000000000000000000000011"); // x = 3
+ z = z & x; // z = 00000000 00000000 00000000 00000001
+
+ // array variable + array variable
+ x = (a, f); // x = 10
+ z = z | x; // z = 00000000 00000000 00000000 00001011
+
+ // =============== Cascading ====================================
+ // cascading array variables
+ x = (a, b, c, d); // x = 00000000 00000001 00000011 00001111
+ z = z & x; // z = 00000000 00000000 00000000 00001011
+
+ // cascading array constants
+ x = ( sc_lv_base( "00000011" ), "00000011", "00000011", "00000011");
+ // x = 00000011 00000011 00000011 00000011
+ z = z | x; // z = 00000011 00000011 00000011 00001011
+
+ // composing array concats
+ x = ( sc_lv_base( "00000011" ), ( sc_lv_base( "11111111" ), "00000011", "00000011"));
+ // x = 00000011 11111111 00000011 00000011
+ z = z | x; // z = 00000011 11111111 00000011 00001011
+
+ // =============== Array (variable) + Scalar ==============================
+ // array variable + scalar constant
+ m = '0';
+ n = '1';
+ x = (a, b, c, d.range (6, 0), m);
+ // x = 00000000 00000001 00000011 00011110
+ z = z | x; // z = 00000011 11111111 00000011 00011111
+
+ k = '1';
+ // array variable + scalar variable
+ x = (a, b, k, c.range (6, 0), x.range (7, 0));
+ // x = 00000000 00000001 10000001 00011110
+ z = z & x; // z = 00000000 00000001 00000001 00011110
+
+ // =============== Null Vector ====================================
+ // null vector - variable
+ kk = ~( sc_lv_base( k ), k); // "00"
+ z = (z.range (31, 2), kk); // z = 00000000 00000001 00000001 00011100
+
+ // null vector - constant
+ kk = ( sc_lv_base( n ), n); // "11"
+ z = (kk, z.range (29, 0)); // z = 11000000 00000001 00000001 00011100
+
+ // =============== Array (constant) + Scalar ==============================
+ // scalar constant + array constant
+ x = ( sc_lv_base( n ), "1111111000000000000000000000011");
+ // x = 01111111 00000000 00000000 00000011
+ z = z | x; // z = 11111111 00000001 00000001 00011111
+
+ // array constant + scalar variable
+ x = ( sc_lv_base( "1111111000000000000000000000011" ), k);
+ // x = 11111110 00000000 00000000 00000111
+ z = z & x; // z = 11111110 00000000 00000000 00000111
+
+ // =============== LHS/RHS of different widths ==============================
+ // lhs and rhs of different widths
+ x = "100001111000000000000000000001111"; // warning should be issued
+ z = z & x;
+ // z = 00001110 00000000 00000000 00000111
+
+ o1 = z.to_int();
+ wait();
+
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.f b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.f
new file mode 100644
index 000000000..2399ece43
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.f
@@ -0,0 +1,4 @@
+rvalue/test.cpp
+rvalue/tb.cpp
+rvalue/monitor.cpp
+rvalue/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.h b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.h
new file mode 100644
index 000000000..5596f1f8d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( test )
+{
+ SC_HAS_PROCESS( test );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Output Data Ports
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ test (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};