diff options
author | Gabe Black <gabeblack@google.com> | 2018-05-24 01:37:55 -0700 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2018-08-08 10:09:54 +0000 |
commit | 16fa8d7cc8c92f5ab879e4cf9c6c0bbb3567860f (patch) | |
tree | 7b6faaacb4574a555e561534aa4a8508c0624c32 /src/systemc/tests/systemc/misc/user_guide/chpt7.2 | |
parent | 7235d3b5211d0ba8f528d930a4c1e7ad62eec51a (diff) | |
download | gem5-16fa8d7cc8c92f5ab879e4cf9c6c0bbb3567860f.tar.xz |
systemc: Import tests from the Accellera systemc distribution.
Change-Id: Iad76b398949a55d768a34d027a2d8e3739953da6
Reviewed-on: https://gem5-review.googlesource.com/10845
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/systemc/tests/systemc/misc/user_guide/chpt7.2')
8 files changed, 657 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt7.2/adder_sub.cpp b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/adder_sub.cpp new file mode 100644 index 000000000..caf7e5c1f --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/adder_sub.cpp @@ -0,0 +1,76 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + adder_sub.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename adder_sub.cc */ +/* This is the implementation file for synchronous process `adder_sub' */ + +#include "adder_sub.h" + +int add(int a, int b) +{ + return (a + b); +} + +void adder_sub::entry() +{ + int sum; + int a, b, c, d; + + while (true) { + // Wait until you get signal to go + do { wait(); } while (adder_sub_ready != true); + // Read inputs + a = Sa.read(); + b = Sb.read(); + c = Sc.read(); + + // Perform the computation. + sum = add(a, b); + sum = add(sum, c); + d = a - b; + + // Write outputs + adder_sub_done.write(true); + Ssum.write(sum); + Sd.write(d); + wait(); + adder_sub_done.write(false); + // Loop back to do { wait(); } while . + } + +} // end of entry function + diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt7.2/adder_sub.h b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/adder_sub.h new file mode 100644 index 000000000..913f1f5f2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/adder_sub.h @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + adder_sub.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename adder_sub.h */ +/* This is the interface file for synchronous process `adder_sub' */ + +#include "systemc.h" + +SC_MODULE( adder_sub ) +{ + SC_HAS_PROCESS( adder_sub ); + + sc_in_clk clk; + + const sc_signal<int>& Sa; //input + const sc_signal<int>& Sb; //input + const sc_signal<int>& Sc; //input + const sc_signal<bool>& adder_sub_ready; //input + sc_signal<int>& Sd; //output + sc_signal<int>& Ssum; //output + sc_signal<bool>& adder_sub_done; //output + + //Constructor + adder_sub(sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& SA, + const sc_signal<int>& SB, + const sc_signal<int>& SC, + const sc_signal<bool>& ADDER_SUB_READY, + sc_signal<int>& SD, + sc_signal<int>& SSUM, + sc_signal<bool>& ADDER_SUB_DONE) + : Sa(SA), Sb(SB), Sc(SC), + adder_sub_ready(ADDER_SUB_READY), + Sd(SD), Ssum(SSUM), adder_sub_done(ADDER_SUB_DONE) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + // Process functionality in member function below + void entry(); +}; + + diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt7.2/chpt7.2.f b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/chpt7.2.f new file mode 100644 index 000000000..e19c1162a --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/chpt7.2.f @@ -0,0 +1,3 @@ +chpt7.2/adder_sub.cpp +chpt7.2/main.cpp +chpt7.2/testbench.cpp diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt7.2/golden/chpt7.2.log b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/golden/chpt7.2.log new file mode 100644 index 000000000..25ff64775 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/golden/chpt7.2.log @@ -0,0 +1,13 @@ +SystemC Simulation +A = 136708339, B = 739981, C = 1795618, D = 135968358, SUM = 139243938 +A = 9096481, B = 158324345, C = 156370665, D = -149227864, SUM = 323791491 +A = 67086517, B = 264870948, C = 252125103, D = -197784431, SUM = 584082568 +A = 35986927, B = 156189122, C = 206347003, D = -120202195, SUM = 398523052 +A = 113459060, B = 75282205, C = 152014781, D = 38176855, SUM = 340756046 +A = 106493306, B = 96640536, C = 38402601, D = 9852770, SUM = 241536443 +A = 182546426, B = 97022397, C = 80174628, D = 85524029, SUM = 359743451 +A = 179563193, B = 205851535, C = 103403428, D = -26288342, SUM = 488818156 +A = 1501295, B = 41700621, C = 124029719, D = -40199326, SUM = 167231635 +A = 96489422, B = 81002361, C = 111989263, D = 15487061, SUM = 289481046 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt7.2/isaac.h b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/isaac.h new file mode 100644 index 000000000..9625be2ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/isaac.h @@ -0,0 +1,272 @@ +#ifndef __ISAAC_HPP +#define __ISAAC_HPP + + +/* + + C++ TEMPLATE VERSION OF Robert J. Jenkins Jr.'s + ISAAC Random Number Generator. + + Ported from vanilla C to to template C++ class + by Quinn Tyler Jackson on 16-23 July 1998. + + quinn@qtj.net + + The function for the expected period of this + random number generator, according to Jenkins is: + + f(a,b) = 2**((a+b*(3+2^^a)-1) + + (where a is ALPHA and b is bitwidth) + + So, for a bitwidth of 32 and an ALPHA of 8, + the expected period of ISAAC is: + + 2^^(8+32*(3+2^^8)-1) = 2^^8295 + + Jackson has been able to run implementations + with an ALPHA as high as 16, or + + 2^^2097263 + +*/ + + +typedef unsigned int UINT32; +const UINT32 GOLDEN_RATIO = UINT32(0x9e3779b9); + + +template <UINT32 ALPHA = (8)> +class QTIsaac +{ + public: + + typedef unsigned char byte; + + struct randctx + { + randctx(void) + { + randrsl = new UINT32[N]; + randmem = new UINT32[N]; + } + + ~randctx(void) + { + delete [] randrsl; + delete [] randmem; + } + + UINT32 randcnt; + UINT32* randrsl; + UINT32* randmem; + UINT32 randa; + UINT32 randb; + UINT32 randc; + }; + + QTIsaac(UINT32 a = 0, UINT32 b = 0, UINT32 c = 0); + virtual ~QTIsaac(void); + + UINT32 rand(void); + virtual void randinit(randctx* ctx, bool bUseSeed); + virtual void srand( + UINT32 a = 0, UINT32 b = 0, UINT32 c = 0, UINT32* s = NULL); + + enum {N = (1<<ALPHA)}; + + protected: + + virtual void isaac(randctx* ctx); + + UINT32 ind(UINT32* mm, UINT32 x); + void rngstep( + UINT32 mix, UINT32& a, UINT32& b, UINT32*& mm, UINT32*& m, + UINT32*& m2, UINT32*& r, UINT32& x, UINT32& y); + virtual void shuffle( + UINT32& a, UINT32& b, UINT32& c, UINT32& d, UINT32& e, UINT32& f, + UINT32& g, UINT32& h); + + private: + randctx m_rc; +}; + + +template<UINT32 ALPHA> +QTIsaac<ALPHA>::QTIsaac(UINT32 a, UINT32 b, UINT32 c) : m_rc() +{ + srand(a, b, c); +} + + +template<UINT32 ALPHA> +QTIsaac<ALPHA>::~QTIsaac(void) +{ + // DO NOTHING +} + + +template<UINT32 ALPHA> +void QTIsaac<ALPHA>::srand(UINT32 a, UINT32 b, UINT32 c, UINT32* s) +{ + for(int i = 0; i < N; i++) + { + m_rc.randrsl[i] = s != NULL ? s[i] : 0; + } + + m_rc.randa = a; + m_rc.randb = b; + m_rc.randc = c; + + randinit(&m_rc, true); +} + + +template<UINT32 ALPHA> +inline UINT32 QTIsaac<ALPHA>::rand(void) +{ + return 0x7fffffff & (!m_rc.randcnt-- ? + (isaac(&m_rc), m_rc.randcnt=(N-1), m_rc.randrsl[m_rc.randcnt]) : + m_rc.randrsl[m_rc.randcnt]); +} + + +template<UINT32 ALPHA> +inline void QTIsaac<ALPHA>::randinit(randctx* ctx, bool bUseSeed) +{ + UINT32 a,b,c,d,e,f,g,h; + int i; + + a = b = c = d = e = f = g = h = GOLDEN_RATIO; + + UINT32* m = (ctx->randmem); + UINT32* r = (ctx->randrsl); + + if(!bUseSeed) + { + ctx->randa = 0; + ctx->randb = 0; + ctx->randc = 0; + } + + // scramble it + for(i=0; i < 4; ++i) + { + shuffle(a,b,c,d,e,f,g,h); + } + + if(bUseSeed) + { + // initialize using the contents of r[] as the seed + + for(i=0; i < N; i+=8) + { + a+=r[i ]; b+=r[i+1]; c+=r[i+2]; d+=r[i+3]; + e+=r[i+4]; f+=r[i+5]; g+=r[i+6]; h+=r[i+7]; + + shuffle(a,b,c,d,e,f,g,h); + + m[i ]=a; m[i+1]=b; m[i+2]=c; m[i+3]=d; + m[i+4]=e; m[i+5]=f; m[i+6]=g; m[i+7]=h; + } + + //do a second pass to make all of the seed affect all of m + + for(i=0; i < N; i += 8) + { + a+=m[i ]; b+=m[i+1]; c+=m[i+2]; d+=m[i+3]; + e+=m[i+4]; f+=m[i+5]; g+=m[i+6]; h+=m[i+7]; + + shuffle(a,b,c,d,e,f,g,h); + + m[i ]=a; m[i+1]=b; m[i+2]=c; m[i+3]=d; + m[i+4]=e; m[i+5]=f; m[i+6]=g; m[i+7]=h; + } + } + else + { + // fill in mm[] with messy stuff + + shuffle(a,b,c,d,e,f,g,h); + + m[i ]=a; m[i+1]=b; m[i+2]=c; m[i+3]=d; + m[i+4]=e; m[i+5]=f; m[i+6]=g; m[i+7]=h; + + } + + isaac(ctx); // fill in the first set of results + ctx->randcnt = N; // prepare to use the first set of results +} + + +template<UINT32 ALPHA> +inline UINT32 QTIsaac<ALPHA>::ind(UINT32* mm, UINT32 x) +{ + return (*(UINT32*)((byte*)(mm) + ((x) & ((N-1)<<2)))); +} + + +template<UINT32 ALPHA> +inline void QTIsaac<ALPHA>::rngstep(UINT32 mix, UINT32& a, UINT32& b, UINT32*& mm, UINT32*& m, UINT32*& m2, UINT32*& r, UINT32& x, UINT32& y) +{ + x = *m; + a = (a^(mix)) + *(m2++); + *(m++) = y = ind(mm,x) + a + b; + *(r++) = b = ind(mm,y>>ALPHA) + x; +} + + +template<UINT32 ALPHA> +inline void QTIsaac<ALPHA>::shuffle(UINT32& a, UINT32& b, UINT32& c, UINT32& d, UINT32& e, UINT32& f, UINT32& g, UINT32& h) +{ + a^=b<<11; d+=a; b+=c; + b^=c>>2; e+=b; c+=d; + c^=d<<8; f+=c; d+=e; + d^=e>>16; g+=d; e+=f; + e^=f<<10; h+=e; f+=g; + f^=g>>4; a+=f; g+=h; + g^=h<<8; b+=g; h+=a; + h^=a>>9; c+=h; a+=b; +} + + +template<UINT32 ALPHA> +inline void QTIsaac<ALPHA>::isaac(randctx* ctx) +{ + UINT32 x,y; + + UINT32* mm = ctx->randmem; + UINT32* r = ctx->randrsl; + + UINT32 a = (ctx->randa); + UINT32 b = (ctx->randb + (++ctx->randc)); + + UINT32* m = mm; + UINT32* m2 = (m+(N/2)); + UINT32* mend = m2; + + for(; m<mend; ) + { + rngstep((a<<13), a, b, mm, m, m2, r, x, y); + rngstep((a>>6) , a, b, mm, m, m2, r, x, y); + rngstep((a<<2) , a, b, mm, m, m2, r, x, y); + rngstep((a>>16), a, b, mm, m, m2, r, x, y); + } + + m2 = mm; + + for(; m2<mend; ) + { + rngstep((a<<13), a, b, mm, m, m2, r, x, y); + rngstep((a>>6) , a, b, mm, m, m2, r, x, y); + rngstep((a<<2) , a, b, mm, m, m2, r, x, y); + rngstep((a>>16), a, b, mm, m, m2, r, x, y); + } + + ctx->randb = b; + ctx->randa = a; +} + + +#endif // __ISAAC_HPP + diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt7.2/main.cpp b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/main.cpp new file mode 100644 index 000000000..745338a04 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/main.cpp @@ -0,0 +1,59 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "testbench.h" +#include "adder_sub.h" + +int sc_main(int ac, char *av[]) +{ + sc_signal<int> a; + sc_signal<int> b; + sc_signal<int> c; + sc_signal<int> d; + sc_signal<int> sum; + sc_signal<bool> ready; + sc_signal<bool> done; + sc_clock clock("Clock", 10, SC_NS, 0.5, 0, SC_NS); + + testbench T("TB", clock, sum, d, done, a, b, c, ready); + adder_sub AS("AS", clock, a, b, c, ready, d, sum, done); + + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt7.2/testbench.cpp b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/testbench.cpp new file mode 100644 index 000000000..bc91bb257 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/testbench.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + testbench.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename testbench.cc */ +/* This is the implementation file for synchronous process `testbench' */ + +#include <math.h> +#include "testbench.h" +#include "isaac.h" + +QTIsaac<8> rng; + +void testbench::entry() +{ + int a, b, c, d; + int sum; + int i; + + for (i=0; i < 10; i++) { + a = rng.rand() & 0x0fffffff; + b = rng.rand() & 0x0fffffff; + c = rng.rand() & 0x0fffffff; + + Sa.write(a); + Sb.write(b); + Sc.write(c); + adder_sub_ready.write(true); + wait(); + adder_sub_ready.write(false); + do { wait(); } while (adder_sub_done != true); + sum = Ssum.read(); + d = Sdiff.read(); + // printf("A = %d, B = %d, C = %d, D = %d, SUM = %d\n", a, b, c, d, sum); + char buf[BUFSIZ]; + sprintf(buf, "A = %d, B = %d, C = %d, D = %d, SUM = %d\n", a, b, c, d, sum); + cout << buf; + } + sc_stop(); + +} // end of entry function + diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt7.2/testbench.h b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/testbench.h new file mode 100644 index 000000000..9e5e2383f --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt7.2/testbench.h @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + testbench.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename testbench.h */ +/* This is the interface file for synchronous process `testbench' */ + +#include "systemc.h" + +SC_MODULE( testbench ) +{ + SC_HAS_PROCESS( testbench ); + + sc_in_clk clk; + + const sc_signal<int>& Ssum; //input + const sc_signal<int>& Sdiff; //input + const sc_signal<bool>& adder_sub_done; //input + sc_signal<int>& Sa; //output + sc_signal<int>& Sb; //output + sc_signal<int>& Sc; //output + sc_signal<bool>& adder_sub_ready; //output + + //Constructor + testbench(sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& SSUM, + const sc_signal<int>& SDIFF, + const sc_signal<bool>& ADDER_SUB_DONE, + sc_signal<int>& SA, + sc_signal<int>& SB, + sc_signal<int>& SC, + sc_signal<bool>& ADDER_SUB_READY) + : Ssum(SSUM), Sdiff(SDIFF), + adder_sub_done(ADDER_SUB_DONE), + Sa(SA), Sb(SB), Sc(SC), adder_sub_ready(ADDER_SUB_READY) + + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + // Process functionality in member function below + void entry(); +}; + + |