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author | Gabe Black <gabeblack@google.com> | 2018-05-24 01:37:55 -0700 |
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committer | Gabe Black <gabeblack@google.com> | 2018-08-08 10:09:54 +0000 |
commit | 16fa8d7cc8c92f5ab879e4cf9c6c0bbb3567860f (patch) | |
tree | 7b6faaacb4574a555e561534aa4a8508c0624c32 /src/systemc/tests/systemc/utils/sc_vector/test01 | |
parent | 7235d3b5211d0ba8f528d930a4c1e7ad62eec51a (diff) | |
download | gem5-16fa8d7cc8c92f5ab879e4cf9c6c0bbb3567860f.tar.xz |
systemc: Import tests from the Accellera systemc distribution.
Change-Id: Iad76b398949a55d768a34d027a2d8e3739953da6
Reviewed-on: https://gem5-review.googlesource.com/10845
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/systemc/tests/systemc/utils/sc_vector/test01')
-rw-r--r-- | src/systemc/tests/systemc/utils/sc_vector/test01/golden/test01.log | 12 | ||||
-rw-r--r-- | src/systemc/tests/systemc/utils/sc_vector/test01/test01.cpp | 84 |
2 files changed, 96 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/utils/sc_vector/test01/golden/test01.log b/src/systemc/tests/systemc/utils/sc_vector/test01/golden/test01.log new file mode 100644 index 000000000..c05a2fb7c --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test01/golden/test01.log @@ -0,0 +1,12 @@ +SystemC Simulation +dut.sub_modules - sc_vector +dut.sub_modules_0 - sc_module +dut.sub_modules_1 - sc_module +dut.sub_modules_2 - sc_module +dut.sub_modules_3 - sc_module +dut.vector_0 - sc_vector +dut.vector_0_0 - sc_in +dut.vector_0_1 - sc_in +dut.vector_0_2 - sc_in +dut.vector_0_3 - sc_in +Program completed diff --git a/src/systemc/tests/systemc/utils/sc_vector/test01/test01.cpp b/src/systemc/tests/systemc/utils/sc_vector/test01/test01.cpp new file mode 100644 index 000000000..47cc9d45a --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test01/test01.cpp @@ -0,0 +1,84 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test01.cpp -- Test sc_vector + + Original Author: Philipp A. Hartmann, OFFIS, 2010-01-10 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +#include "sysc/utils/sc_vector.h" +using sc_core::sc_vector; + +SC_MODULE( sub_module ) +{ + sc_in<bool> in; + SC_CTOR(sub_module) {} +}; + +SC_MODULE( module ) +{ + // vector of sub-modules + sc_vector< sub_module > m_sub_vec; + + // vector of ports + sc_vector< sc_in<bool> > in_vec; + + module( sc_core::sc_module_name, unsigned n_sub ) + : m_sub_vec( "sub_modules", n_sub ) // set name prefix, and create sub-modules + // , in_vec() // use default constructor + // , in_vec( "in_vec" ) // set name prefix + { + // delayed initialisation of port vector + // here with default prefix sc_core::sc_gen_unique_name("vector") + in_vec.init( n_sub ); + + // bind ports of sub-modules -- sc_assemble_vector + sc_assemble_vector( m_sub_vec, &sub_module::in ).bind( in_vec ); + } +}; + +int sc_main(int , char* []) +{ + module m("dut", 4); + + std::vector<sc_object*> children = m.get_child_objects(); + + for (size_t i=0; i<children.size(); ++i ) + cout << children[i]->name() << " - " + << children[i]->kind() + << endl; + + cout << "Program completed" << endl; + return 0; +} |