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| author | Gabe Black <gabeblack@google.com> | 2019-03-14 05:33:51 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-03-29 22:46:00 +0000 |
| commit | 2a98a994df296f818b05da90ba073d879562da04 (patch) | |
| tree | 18d0f98c27c157e1d1f9884031d1ff22f10e0fca /src/systemc/tlm_bridge/TlmBridge.py | |
| parent | b2efb725921c9387852f439ad20964c428072dd7 (diff) | |
| download | gem5-2a98a994df296f818b05da90ba073d879562da04.tar.xz | |
systemc: Templatize the gem5/TLM bridge SimObjects.
The C++ side is templated, and there are python versions for each
(currently two) width of bridge supported.
Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17234
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/systemc/tlm_bridge/TlmBridge.py')
| -rw-r--r-- | src/systemc/tlm_bridge/TlmBridge.py | 40 |
1 files changed, 34 insertions, 6 deletions
diff --git a/src/systemc/tlm_bridge/TlmBridge.py b/src/systemc/tlm_bridge/TlmBridge.py index d2dff8600..dcc545280 100644 --- a/src/systemc/tlm_bridge/TlmBridge.py +++ b/src/systemc/tlm_bridge/TlmBridge.py @@ -29,9 +29,10 @@ from m5.objects.SystemC import SystemC_ScModule from m5.params import * from m5.proxy import * -class Gem5ToTlmBridge(SystemC_ScModule): - type = 'Gem5ToTlmBridge' - cxx_class = 'sc_gem5::Gem5ToTlmBridge' +class Gem5ToTlmBridgeBase(SystemC_ScModule): + type = 'Gem5ToTlmBridgeBase' + abstract = True + cxx_class = 'sc_gem5::Gem5ToTlmBridgeBase' cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh' system = Param.System(Parent.any, "system") @@ -41,12 +42,39 @@ class Gem5ToTlmBridge(SystemC_ScModule): addr_ranges = VectorParam.AddrRange([], 'Addresses served by this port\'s TLM side') -class TlmToGem5Bridge(SystemC_ScModule): - type = 'TlmToGem5Bridge' - cxx_class = 'sc_gem5::TlmToGem5Bridge' +class TlmToGem5BridgeBase(SystemC_ScModule): + type = 'TlmToGem5BridgeBase' + abstract = True + cxx_class = 'sc_gem5::TlmToGem5BridgeBase' cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh' system = Param.System(Parent.any, "system") gem5 = MasterPort('gem5 master port') tlm = SlavePort('TLM target socket') + + +class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase): + type = 'Gem5ToTlmBridge32' + cxx_template_params = [ 'unsigned int BITWIDTH' ] + cxx_class = 'sc_gem5::Gem5ToTlmBridge<32>' + cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh' + +class Gem5ToTlmBridge64(Gem5ToTlmBridgeBase): + type = 'Gem5ToTlmBridge64' + cxx_template_params = [ 'unsigned int BITWIDTH' ] + cxx_class = 'sc_gem5::Gem5ToTlmBridge<64>' + cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh' + + +class TlmToGem5Bridge32(TlmToGem5BridgeBase): + type = 'TlmToGem5Bridge32' + cxx_template_params = [ 'unsigned int BITWIDTH' ] + cxx_class = 'sc_gem5::TlmToGem5Bridge<32>' + cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh' + +class TlmToGem5Bridge64(TlmToGem5BridgeBase): + type = 'TlmToGem5Bridge64' + cxx_template_params = [ 'unsigned int BITWIDTH' ] + cxx_class = 'sc_gem5::TlmToGem5Bridge<64>' + cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh' |