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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-03-29 13:02:05 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-04-10 08:41:53 +0000 |
| commit | daa9dcbc0c3fe4e5014855c8b31f1cfeb5f0af91 (patch) | |
| tree | 65b0e6feced44355aa991fa47ab892a1d5e2f50f /src/systemc | |
| parent | 7f9c98472c97f8f71f71c7386496af67fc886d03 (diff) | |
| download | gem5-daa9dcbc0c3fe4e5014855c8b31f1cfeb5f0af91.tar.xz | |
cpu: O3 switchFreeList checking VecElems instead of FloatRegs
Vector elements should be checked instead of floats since those are the
ones mapped to the vector registers.
Change-Id: I36088ab90e63720d846fcf5b43360da105b6c736
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/systemc')
0 files changed, 0 insertions, 0 deletions