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| author | Ani Udipi <ani.udipi@arm.com> | 2013-11-01 11:56:16 -0400 |
|---|---|---|
| committer | Ani Udipi <ani.udipi@arm.com> | 2013-11-01 11:56:16 -0400 |
| commit | d4cf009b95d34b75408363bc085c2e9e9de458d9 (patch) | |
| tree | 01825a265f0e48f850f5ef4d33dc8e03932f2d3f /src/unittest/genini.py | |
| parent | 0e6ced5c4f0c0e2f35dcbdfe4797215f4c7b0e8e (diff) | |
| download | gem5-d4cf009b95d34b75408363bc085c2e9e9de458d9.tar.xz | |
mem: Add tRAS parameter to the DRAM controller model
This patch adds an explicit tRAS parameter to the DRAM controller
model. Previously tRAS was, rather conservatively, assumed to be tRCD
+ tCL + tRP. The default values for tRAS are chosen to match the
previous behaviour and will be updated later.
Diffstat (limited to 'src/unittest/genini.py')
0 files changed, 0 insertions, 0 deletions