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authorMitch Hayenga <mitch.hayenga+gem5@gmail.com>2014-01-29 23:21:26 -0600
committerMitch Hayenga <mitch.hayenga+gem5@gmail.com>2014-01-29 23:21:26 -0600
commit771c864bf407b57bf91896f38e989e8a36cd9cd1 (patch)
treecc0f63f933915a9e58ec2420535c67667af5a180 /src/unittest
parent95735e10e7ea85320ee39c15a4132eece8417af4 (diff)
downloadgem5-771c864bf407b57bf91896f38e989e8a36cd9cd1.tar.xz
mem: Allowed tagged instruction prefetching in stride prefetcher
For systems with a tightly coupled L2, a stride-based prefetcher may observe access requests from both instruction and data L1 caches. However, the PC address of an instruction miss gives no relevant training information to the stride based prefetcher(there is no stride to train). In theses cases, its better if the L2 stride prefetcher simply reverted back to a simple N-block ahead prefetcher. This patch enables this option. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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