Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.

5 files changed, 30 insertions, 25 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 0669a7de4..de8499ef5 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -150,48 +150,53 @@ class BaseCPU(MemObject):
 
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
-    _mem_ports = []
+    _cached_ports = []
+    if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
+        _cached_ports = ["itb.walker.port", "dtb.walker.port"]
+
+    _uncached_ports = []
     if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
-        _mem_ports = ["itb.walker.port",
-                      "dtb.walker.port",
-                      "interrupts.pio",
-                      "interrupts.int_port"]
+        _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
+
+    def connectCachedPorts(self, bus):
+        for p in self._cached_ports:
+            exec('self.%s = bus.port' % p)
 
-    if buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']:
-        _mem_ports = ["itb.walker.port",
-                      "dtb.walker.port"]
+    def connectUncachedPorts(self, bus):
+        for p in self._uncached_ports:
+            exec('self.%s = bus.port' % p)
 
-    def connectMemPorts(self, bus):
-        for p in self._mem_ports:
-            if p != 'physmem_port':
-                exec('self.%s = bus.port' % p)
+    def connectAllPorts(self, cached_bus, uncached_bus = None):
+        self.connectCachedPorts(cached_bus)
+        if not uncached_bus:
+            uncached_bus = cached_bus
+        self.connectUncachedPorts(uncached_bus)
 
     def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
-        assert(len(self._mem_ports) < 8)
+        assert(len(self._cached_ports) < 7)
         self.icache = ic
         self.dcache = dc
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
-        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
         if buildEnv['FULL_SYSTEM']:
             if buildEnv['TARGET_ISA'] == 'x86':
                 self.itb_walker_cache = iwc
                 self.dtb_walker_cache = dwc
                 self.itb.walker.port = iwc.cpu_side
                 self.dtb.walker.port = dwc.cpu_side
-                self._mem_ports += ["itb_walker_cache.mem_side", \
-                                    "dtb_walker_cache.mem_side"]
-                self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
+                self._cached_ports += ["itb_walker_cache.mem_side", \
+                                       "dtb_walker_cache.mem_side"]
             elif buildEnv['TARGET_ISA'] == 'arm':
-                self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
+                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
         self.toL2Bus = Bus()
-        self.connectMemPorts(self.toL2Bus)
+        self.connectCachedPorts(self.toL2Bus)
         self.l2cache = l2c
         self.l2cache.cpu_side = self.toL2Bus.port
-        self._mem_ports = ['l2cache.mem_side']
+        self._cached_ports = ['l2cache.mem_side']
 
     if buildEnv['TARGET_ISA'] == 'mips':
         CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index d6db346d4..8e25891e7 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -46,7 +46,7 @@ class InOrderCPU(BaseCPU):
     dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = ['icache_port', 'dcache_port']
+    _cached_ports = ['icache_port', 'dcache_port']
 
     predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
     localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 38fee369c..f7602cb86 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -55,7 +55,7 @@ class DerivO3CPU(BaseCPU):
     cachePorts = Param.Unsigned(200, "Cache Ports")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port']
+    _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port']
 
     decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
     renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 3d72f4098..a4d807f86 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -37,5 +37,5 @@ class AtomicSimpleCPU(BaseSimpleCPU):
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")
-    _mem_ports = BaseSimpleCPU._mem_ports + \
-                    ['icache_port', 'dcache_port', 'physmem_port']
+    _cached_ports = BaseSimpleCPU._cached_ports + \
+                    ['icache_port', 'dcache_port']
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 6b83c41aa..8d6888f72 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -33,4 +33,4 @@ class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
+    _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port', 'dcache_port']