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authorGabe Black <gblack@eecs.umich.edu>2007-07-20 14:53:38 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-20 14:53:38 -0700
commit0baae59c0902d17158fc592bf4dbd0e97fe6d33e (patch)
tree1350648772bdc4f5ef85d77fee9de50c1132c8f0 /src
parent0781609693ef3ec0ee12aa6031c62d8a2e67d49c (diff)
downloadgem5-0baae59c0902d17158fc592bf4dbd0e97fe6d33e.tar.xz
Fix carry flag for subtracts, and clean up code slightly.
--HG-- extra : convert_revision : 668f5d5aeba888488b41284de6c72a0d055c4ef4
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/isa/microops/regop.isa42
1 files changed, 27 insertions, 15 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index f833f89be..a0e8adc9a 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -309,7 +309,7 @@ let {{
exec_output = ""
# A function which builds the C++ classes that implement the microops
- def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck, elseCode):
+ def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"):
global header_output
global decoder_output
global exec_output
@@ -331,7 +331,7 @@ let {{
# This creates a python representations of a microop which are a cross
# product of reg/immediate and flag/no flag versions.
- def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False, elseCode=";"):
+ def defineMicroRegOp(mnemonic, code, subtract = False, cc=False, elseCode=";"):
Name = mnemonic
name = mnemonic.lower()
@@ -342,6 +342,11 @@ let {{
regCode = matcher.sub("SrcReg2", code)
immCode = matcher.sub("imm8", code)
+ if subtract:
+ secondSrc = "-op2, true"
+ else:
+ secondSrc = "op2"
+
if not cc:
flagCode = genCCFlagBits % secondSrc
condCode = "true"
@@ -360,8 +365,9 @@ let {{
microopClasses[name] = RegOpChild
- setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true", elseCode);
- setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode, elseCode);
+ setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
+ setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
+ flagCode = regFlagCode, condCheck = condCode, elseCode = elseCode);
class RegOpChildImm(RegOpImm):
mnemonic = name + 'i'
@@ -371,17 +377,19 @@ let {{
microopClasses[name + 'i'] = RegOpChildImm
- setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true", elseCode);
- setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode, elseCode);
+ setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
+ setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
+ flagCode = immFlagCode, condCheck = condCode, elseCode = elseCode);
defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
- defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
+ defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
- defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
+ defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
- defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2')
+ defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True)
+ defineMicroRegOp('mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)')
defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
elseCode='DestReg=DestReg;', cc=True)
@@ -405,8 +413,9 @@ let {{
microopClasses[name] = RegOpChild
- setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true", elseCode);
- setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits, elseCode);
+ setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
+ setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
+ condCheck = checkCCFlagBits, elseCode = elseCode);
class RegOpChildImm(RegOpImm):
mnemonic = name + 'i'
@@ -416,8 +425,9 @@ let {{
microopClasses[name + 'i'] = RegOpChildImm
- setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true", elseCode);
- setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits, elseCode);
+ setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
+ setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
+ condCheck = checkCCFlagBits, elseCode = elseCode);
defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;")
@@ -434,7 +444,7 @@ let {{
microopClasses[name] = RegOpChild
- setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true", ";");
+ setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
@@ -450,11 +460,13 @@ let {{
microopClasses[name] = RegOpChild
- setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true", ";");
+ setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
defineMicroRegOpImm('Sext', '''
IntReg val = SrcReg1;
int sign_bit = bits(val, imm8-1, imm8-1);
val = sign_bit ? (val | ~mask(imm8)) : val;
DestReg = merge(DestReg, val, dataSize);''')
+
+ defineMicroRegOpImm('Zext', 'DestReg = bits(SrcReg1, imm8-1, 0);')
}};