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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:24 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:24 -0600 |
| commit | 0f2bbe15ddfeb3894726c19e09ed23f7027df1cb (patch) | |
| tree | b7762fe7e63813f98532f5957e3121914db905e2 /src | |
| parent | c779af4e1295c9649ffbbd297ed535bead1cc885 (diff) | |
| download | gem5-0f2bbe15ddfeb3894726c19e09ed23f7027df1cb.tar.xz | |
ARM: Keep the warnings to a minimum.
These warnings still need to be addresses, but pages of them is
counterproductive.
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa.cc | 14 | ||||
| -rw-r--r-- | src/dev/arm/RealView.py | 2 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 0ba62f08d..20cddcff1 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -180,10 +180,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) } switch (misc_reg) { case MISCREG_CLIDR: - warn("The clidr register always reports 0 caches.\n"); + warn_once("The clidr register always reports 0 caches.\n"); break; case MISCREG_CCSIDR: - warn("The ccsidr register isn't implemented and " + warn_once("The ccsidr register isn't implemented and " "always reads as 0.\n"); break; case MISCREG_ID_PFR0: @@ -268,7 +268,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) } break; case MISCREG_CSSELR: - warn("The csselr register isn't implemented.\n"); + warn_once("The csselr register isn't implemented.\n"); break; case MISCREG_FPSCR: { @@ -319,7 +319,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) return; case MISCREG_TLBIALLIS: case MISCREG_TLBIALL: - warn("Need to flush all TLBs in MP\n"); + warn_once("Need to flush all TLBs in MP\n"); tc->getITBPtr()->flushAll(); tc->getDTBPtr()->flushAll(); return; @@ -331,7 +331,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) return; case MISCREG_TLBIMVAIS: case MISCREG_TLBIMVA: - warn("Need to flush all TLBs in MP\n"); + warn_once("Need to flush all TLBs in MP\n"); tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), bits(newVal, 7,0)); tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), @@ -339,13 +339,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) return; case MISCREG_TLBIASIDIS: case MISCREG_TLBIASID: - warn("Need to flush all TLBs in MP\n"); + warn_once("Need to flush all TLBs in MP\n"); tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); return; case MISCREG_TLBIMVAAIS: case MISCREG_TLBIMVAA: - warn("Need to flush all TLBs in MP\n"); + warn_once("Need to flush all TLBs in MP\n"); tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); return; diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 0b29a8270..b529fdfd4 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -100,7 +100,7 @@ class RealViewPBX(RealView): timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) - l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") + l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x4000000) dmac_fake = AmbaFake(pio_addr=0x10030000) uart1_fake = AmbaFake(pio_addr=0x1000a000) |