diff options
| author | Derek Hower <drh5@cs.wisc.edu> | 2009-07-13 14:49:51 -0500 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2009-07-13 14:49:51 -0500 |
| commit | 100da6b3267b4e3d6834cd872502b8303d289d17 (patch) | |
| tree | 1a1427989468e5b6e5f8a1c1c7bb96b3bbdb6f2c /src | |
| parent | d51445490d9f7ccd09d7003f4360044422bd7b57 (diff) | |
| parent | 60577eb4caff66a756f260bff6bf3bf8cb7edcba (diff) | |
| download | gem5-100da6b3267b4e3d6834cd872502b8303d289d17.tar.xz | |
merge
Diffstat (limited to 'src')
152 files changed, 2604 insertions, 6934 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript index 0d801fcad..6dfcba185 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -46,6 +46,7 @@ isa_switch_hdrs = Split(''' arguments.hh faults.hh interrupts.hh + isa.hh isa_traits.hh kernel_stats.hh locked_mem.hh @@ -54,7 +55,7 @@ isa_switch_hdrs = Split(''' mt.hh process.hh predecoder.hh - regfile.hh + registers.hh remote_gdb.hh stacktrace.hh tlb.hh diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 069db2551..e3701d2a4 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -34,12 +34,10 @@ Import('*') if env['TARGET_ISA'] == 'alpha': Source('ev5.cc') Source('faults.cc') - Source('floatregfile.cc') - Source('intregfile.cc') Source('ipr.cc') - Source('miscregfile.cc') + Source('isa.cc') Source('pagetable.cc') - Source('regfile.cc') + Source('regredir.cc') Source('remote_gdb.cc') Source('tlb.cc') Source('utility.cc') diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index adbebb346..bf641d2fe 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -127,18 +127,6 @@ zeroRegisters(CPU *cpu) cpu->thread->setFloatReg(ZeroReg, 0.0); } -int -MiscRegFile::getInstAsid() -{ - return ITB_ASN_ASN(ipr[IPR_ITB_ASN]); -} - -int -MiscRegFile::getDataAsid() -{ - return DTB_ASN_ASN(ipr[IPR_DTB_ASN]); -} - #endif //////////////////////////////////////////////////////////////////////// @@ -158,7 +146,7 @@ initIPRs(ThreadContext *tc, int cpuId) } MiscReg -MiscRegFile::readIpr(int idx, ThreadContext *tc) +ISA::readIpr(int idx, ThreadContext *tc) { uint64_t retval = 0; // return value, default 0 @@ -270,7 +258,7 @@ int break_ipl = -1; #endif void -MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) +ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) { uint64_t old; diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh index a135ac506..5abc7e57f 100644 --- a/src/arch/alpha/ev5.hh +++ b/src/arch/alpha/ev5.hh @@ -35,6 +35,8 @@ #include "arch/alpha/isa_traits.hh" +class ThreadContext; + namespace AlphaISA { const uint64_t AsnMask = ULL(0xff); @@ -106,6 +108,8 @@ inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; } const Addr PalBase = 0x4000; const Addr PalMax = 0x10000; +void copyIprs(ThreadContext *src, ThreadContext *dest); + } // namespace AlphaISA #endif // __ARCH_ALPHA_EV5_HH__ diff --git a/src/arch/alpha/floatregfile.cc b/src/arch/alpha/floatregfile.cc deleted file mode 100644 index 192b0f1d4..000000000 --- a/src/arch/alpha/floatregfile.cc +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Gabe Black - * Kevin Lim - */ - -#include <cstring> - -#include "arch/alpha/floatregfile.hh" -#include "sim/serialize.hh" - -namespace AlphaISA { -void -FloatRegFile::clear() -{ - std::memset(d, 0, sizeof(d)); -} - -void -FloatRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(q, NumFloatRegs); -} - -void -FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(q, NumFloatRegs); -} - -} // namespace AlphaISA diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh deleted file mode 100644 index f6abb1f86..000000000 --- a/src/arch/alpha/floatregfile.hh +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Gabe Black - */ - -#ifndef __ARCH_ALPHA_FLOATREGFILE_HH__ -#define __ARCH_ALPHA_FLOATREGFILE_HH__ - -#include <iosfwd> -#include <string> - -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/types.hh" - -class Checkpoint; - -namespace AlphaISA { - -const int SingleWidth = 32; -const int SingleBytes = SingleWidth / 4; -const int DoubleWidth = 64; -const int DoubleBytes = DoubleWidth / 4; -const int QuadWidth = 128; -const int QuadBytes = QuadWidth / 4; - -class FloatRegFile -{ - public: - static const int regWidth = DoubleWidth; - - union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - }; - - void clear(); - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - - FloatReg - readReg(int floatReg) - { - return d[floatReg]; - } - - FloatReg - readReg(int floatReg, int width) - { - return readReg(floatReg); - } - - FloatRegBits - readRegBits(int floatReg) - { - return q[floatReg]; - } - - FloatRegBits - readRegBits(int floatReg, int width) - { - return readRegBits(floatReg); - } - - void - setReg(int floatReg, const FloatReg &val) - { - d[floatReg] = val; - } - - void - setReg(int floatReg, const FloatReg &val, int width) - { - setReg(floatReg, val); - } - - void - setRegBits(int floatReg, const FloatRegBits &val) - { - q[floatReg] = val; - } - - void - setRegBits(int floatReg, const FloatRegBits &val, int width) - { - setRegBits(floatReg, val); - } - -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_FLOATREGFILE_HH__ diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh deleted file mode 100644 index 3aa7d92c4..000000000 --- a/src/arch/alpha/intregfile.hh +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Gabe Black - */ - -#ifndef __ARCH_ALPHA_INTREGFILE_HH__ -#define __ARCH_ALPHA_INTREGFILE_HH__ - -#include <iosfwd> -#include <string> - -#include "arch/alpha/types.hh" - -class Checkpoint; - -namespace AlphaISA { - -// redirected register map, really only used for the full system case. -extern const int reg_redir[NumIntRegs]; - -class IntRegFile -{ - protected: - IntReg regs[NumIntRegs]; - - public: - IntReg - readReg(int intReg) - { - return regs[intReg]; - } - - void - setReg(int intReg, const IntReg &val) - { - regs[intReg] = val; - } - - void clear(); - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_INTREGFILE_HH__ diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/isa.cc index d52d900fd..eee391a0d 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -25,20 +25,18 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Steve Reinhardt - * Gabe Black - * Kevin Lim + * Authors: Gabe Black */ -#include <cassert> - -#include "arch/alpha/miscregfile.hh" +#include "arch/alpha/isa.hh" #include "base/misc.hh" +#include "cpu/thread_context.hh" -namespace AlphaISA { +namespace AlphaISA +{ void -MiscRegFile::serialize(std::ostream &os) +ISA::serialize(std::ostream &os) { SERIALIZE_SCALAR(fpcr); SERIALIZE_SCALAR(uniq); @@ -48,7 +46,7 @@ MiscRegFile::serialize(std::ostream &os) } void -MiscRegFile::unserialize(Checkpoint *cp, const std::string §ion) +ISA::unserialize(Checkpoint *cp, const std::string §ion) { UNSERIALIZE_SCALAR(fpcr); UNSERIALIZE_SCALAR(uniq); @@ -57,15 +55,9 @@ MiscRegFile::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); } -MiscRegFile::MiscRegFile(BaseCPU *_cpu) -{ - cpu = _cpu; - initializeIprTable(); -} - MiscReg -MiscRegFile::readRegNoEffect(int misc_reg, ThreadID tid) +ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -85,7 +77,7 @@ MiscRegFile::readRegNoEffect(int misc_reg, ThreadID tid) } MiscReg -MiscRegFile::readReg(int misc_reg, ThreadContext *tc, ThreadID tid) +ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -104,7 +96,7 @@ MiscRegFile::readReg(int misc_reg, ThreadContext *tc, ThreadID tid) } void -MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) +ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -130,8 +122,8 @@ MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) } void -MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, - ThreadID tid) +ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, + ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -155,4 +147,4 @@ MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, } } -} // namespace AlphaISA +} diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh new file mode 100644 index 000000000..622d1da4c --- /dev/null +++ b/src/arch/alpha/isa.hh @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_ALPHA_ISA_HH__ +#define __ARCH_ALPHA_ISA_HH__ + +#include <string> +#include <iostream> + +#include "arch/alpha/registers.hh" +#include "arch/alpha/types.hh" +#include "base/types.hh" + +class BaseCPU; +class Checkpoint; +class EventManager; +class ThreadContext; + +namespace AlphaISA +{ + class ISA + { + public: + typedef uint64_t InternalProcReg; + + protected: + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + int intr_flag; + + InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs + + protected: + InternalProcReg readIpr(int idx, ThreadContext *tc); + void setIpr(int idx, InternalProcReg val, ThreadContext *tc); + + public: + + MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); + MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); + + void setMiscRegNoEffect(int misc_reg, const MiscReg &val, + ThreadID tid = 0); + void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, + ThreadID tid = 0); + + void + clear() + { + fpcr = 0; + uniq = 0; + lock_flag = 0; + lock_addr = 0; + intr_flag = 0; + } + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + + void reset(std::string core_name, ThreadID num_threads, + unsigned num_vpes, BaseCPU *_cpu) + { } + + + void expandForMultithreading(ThreadID num_threads, unsigned num_vpes) + { } + + int + flattenIntIndex(int reg) + { + return reg; + } + + int + flattenFloatIndex(int reg) + { + return reg; + } + + ISA() + { + clear(); + initializeIprTable(); + } + }; +} + +#endif diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index aea44976c..2a0699354 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -55,6 +55,8 @@ output header {{ output decoder {{ #include <cmath> +#include "arch/alpha/registers.hh" +#include "arch/alpha/regredir.hh" #include "base/cprintf.hh" #include "base/fenv.hh" #include "base/loader/symtab.hh" @@ -68,9 +70,10 @@ using namespace AlphaISA; output exec {{ #include <math.h> +#include "arch/alpha/regredir.hh" #include "base/cp_annotate.hh" #include "sim/pseudo_inst.hh" -#include "arch/alpha/ipr.hh" +#include "arch/alpha/registers.hh" #include "base/fenv.hh" #include "config/ss_compatible_fp.hh" #include "cpu/base.hh" diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index c8d6f33f9..66c240ef3 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -34,8 +34,6 @@ namespace LittleEndianGuest {} -#include "arch/alpha/ipr.hh" -#include "arch/alpha/max_inst_regs.hh" #include "arch/alpha/types.hh" #include "base/types.hh" #include "config/full_system.hh" @@ -45,16 +43,6 @@ class StaticInstPtr; namespace AlphaISA { using namespace LittleEndianGuest; -using AlphaISAInst::MaxInstSrcRegs; -using AlphaISAInst::MaxInstDestRegs; - -// These enumerate all the registers for dependence tracking. -enum DependenceTags { - // 0..31 are the integer regs 0..31 - // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) - FP_Base_DepTag = 40, - Ctrl_Base_DepTag = 72 -}; StaticInstPtr decodeInst(ExtMachInst); @@ -128,36 +116,6 @@ enum mode_type // Constants Related to the number of registers enum { - NumIntArchRegs = 32, - NumPALShadowRegs = 8, - NumFloatArchRegs = 32, - // @todo: Figure out what this number really should be. - NumMiscArchRegs = 77, - - NumIntRegs = NumIntArchRegs + NumPALShadowRegs, - NumFloatRegs = NumFloatArchRegs, - NumMiscRegs = NumMiscArchRegs, - - TotalNumRegs = - NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs, - - TotalDataRegs = NumIntRegs + NumFloatRegs, - - // semantically meaningful register indices - ZeroReg = 31, // architecturally meaningful - // the rest of these depend on the ABI - StackPointerReg = 30, - GlobalPointerReg = 29, - ProcedureValueReg = 27, - ReturnAddressReg = 26, - ReturnValueReg = 0, - FramePointerReg = 15, - - SyscallNumReg = 0, - FirstArgumentReg = 16, - SyscallPseudoReturnReg = 20, - SyscallSuccessReg = 19, - LogVMPageSize = 13, // 8K bytes VMPageSize = (1 << LogVMPageSize), diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh index e8928ba08..86958e4c5 100644 --- a/src/arch/alpha/locked_mem.hh +++ b/src/arch/alpha/locked_mem.hh @@ -45,7 +45,7 @@ * to do these manipulations based on the physical address. */ -#include "arch/alpha/miscregfile.hh" +#include "arch/alpha/registers.hh" #include "base/misc.hh" #include "mem/request.hh" diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh deleted file mode 100644 index 0d95e5a6d..000000000 --- a/src/arch/alpha/miscregfile.hh +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Gabe Black - */ - -#ifndef __ARCH_ALPHA_MISCREGFILE_HH__ -#define __ARCH_ALPHA_MISCREGFILE_HH__ - -#include <iosfwd> - -#include "arch/alpha/ipr.hh" -#include "arch/alpha/types.hh" -#include "base/types.hh" -#include "sim/serialize.hh" - -class Checkpoint; -class ThreadContext; -class BaseCPU; - -namespace AlphaISA { - -enum MiscRegIndex -{ - MISCREG_FPCR = NumInternalProcRegs, - MISCREG_UNIQ, - MISCREG_LOCKFLAG, - MISCREG_LOCKADDR, - MISCREG_INTR -}; - -class MiscRegFile -{ - public: - friend class RegFile; - typedef uint64_t InternalProcReg; - - protected: - uint64_t fpcr; // floating point condition codes - uint64_t uniq; // process-unique register - bool lock_flag; // lock flag for LL/SC - Addr lock_addr; // lock address for LL/SC - int intr_flag; - - InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs - - BaseCPU *cpu; - - protected: - InternalProcReg readIpr(int idx, ThreadContext *tc); - void setIpr(int idx, InternalProcReg val, ThreadContext *tc); - - public: - MiscRegFile() - { - initializeIprTable(); - } - - MiscRegFile(BaseCPU *cpu); - - // These functions should be removed once the simplescalar cpu - // model has been replaced. - int getInstAsid(); - int getDataAsid(); - - MiscReg readRegNoEffect(int misc_reg, ThreadID tid = 0); - MiscReg readReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); - - void setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0); - void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, - ThreadID tid = 0); - - void - clear() - { - fpcr = 0; - uniq = 0; - lock_flag = 0; - lock_addr = 0; - intr_flag = 0; - } - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - - void reset(std::string core_name, ThreadID num_threads, - unsigned num_vpes, BaseCPU *_cpu) - { } - - - void expandForMultithreading(ThreadID num_threads, unsigned num_vpes) - { } - - -}; - -void copyIprs(ThreadContext *src, ThreadContext *dest); - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_MISCREGFILE_HH__ diff --git a/src/arch/alpha/mmaped_ipr.hh b/src/arch/alpha/mmaped_ipr.hh index af2469ca7..99f8aeb06 100644 --- a/src/arch/alpha/mmaped_ipr.hh +++ b/src/arch/alpha/mmaped_ipr.hh @@ -37,8 +37,11 @@ * ISA-specific helper functions for memory mapped IPR accesses. */ +#include "base/types.hh" #include "mem/packet.hh" +class ThreadContext; + namespace AlphaISA { inline Tick diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc deleted file mode 100644 index b3aa55b19..000000000 --- a/src/arch/alpha/regfile.cc +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Gabe Black - * Kevin Lim - */ - -#include "arch/alpha/regfile.hh" -#include "cpu/thread_context.hh" - -using namespace std; - -namespace AlphaISA { - -void -RegFile::serialize(EventManager *em, ostream &os) -{ - intRegFile.serialize(os); - floatRegFile.serialize(os); - miscRegFile.serialize(os); - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); -#if FULL_SYSTEM - SERIALIZE_SCALAR(intrflag); -#endif -} - -void -RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) -{ - intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); - miscRegFile.unserialize(cp, section); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); -#if FULL_SYSTEM - UNSERIALIZE_SCALAR(intrflag); -#endif -} - -void -copyRegs(ThreadContext *src, ThreadContext *dest) -{ - // First loop through the integer registers. - for (int i = 0; i < NumIntRegs; ++i) - dest->setIntReg(i, src->readIntReg(i)); - - // Then loop through the floating point registers. - for (int i = 0; i < NumFloatRegs; ++i) - dest->setFloatRegBits(i, src->readFloatRegBits(i)); - - // Copy misc. registers - copyMiscRegs(src, dest); - - // Lastly copy PC/NPC - dest->setPC(src->readPC()); - dest->setNextPC(src->readNextPC()); -} - -void -copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - dest->setMiscRegNoEffect(MISCREG_FPCR, - src->readMiscRegNoEffect(MISCREG_FPCR)); - dest->setMiscRegNoEffect(MISCREG_UNIQ, - src->readMiscRegNoEffect(MISCREG_UNIQ)); - dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, - src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); - dest->setMiscRegNoEffect(MISCREG_LOCKADDR, - src->readMiscRegNoEffect(MISCREG_LOCKADDR)); - - copyIprs(src, dest); -} - -} // namespace AlphaISA diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh deleted file mode 100644 index cbd3657f7..000000000 --- a/src/arch/alpha/regfile.hh +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_ALPHA_REGFILE_HH__ -#define __ARCH_ALPHA_REGFILE_HH__ - -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/floatregfile.hh" -#include "arch/alpha/intregfile.hh" -#include "arch/alpha/miscregfile.hh" -#include "arch/alpha/types.hh" -#include "arch/alpha/mt.hh" -#include "sim/faults.hh" - -#include <string> - -//XXX These should be implemented by someone who knows the alpha stuff better - -class Checkpoint; -class EventManager; -class ThreadContext; - -namespace AlphaISA { - -class RegFile { - protected: - Addr pc; // program counter - Addr npc; // next-cycle program counter - Addr nnpc; // next next-cycle program counter - - public: - Addr - readPC() - { - return pc; - } - - void - setPC(Addr val) - { - pc = val; - } - - Addr - readNextPC() - { - return npc; - } - - void - setNextPC(Addr val) - { - npc = val; - } - - Addr - readNextNPC() - { - return npc + sizeof(MachInst); - } - - void - setNextNPC(Addr val) - { } - - protected: - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file - - public: -#if FULL_SYSTEM - int intrflag; // interrupt flag - - int - instAsid() - { - return miscRegFile.getInstAsid(); - } - - int - dataAsid() - { - return miscRegFile.getDataAsid(); - } -#endif // FULL_SYSTEM - - void - clear() - { - intRegFile.clear(); - floatRegFile.clear(); - miscRegFile.clear(); - } - - MiscReg - readMiscRegNoEffect(int miscReg) - { - return miscRegFile.readRegNoEffect(miscReg); - } - - MiscReg - readMiscReg(int miscReg, ThreadContext *tc) - { - return miscRegFile.readReg(miscReg, tc); - } - - void - setMiscRegNoEffect(int miscReg, const MiscReg &val) - { - miscRegFile.setRegNoEffect(miscReg, val); - } - - void - setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc) - { - miscRegFile.setReg(miscReg, val, tc); - } - - FloatReg - readFloatReg(int floatReg) - { - return floatRegFile.d[floatReg]; - } - - FloatReg - readFloatReg(int floatReg, int width) - { - return readFloatReg(floatReg); - } - - FloatRegBits - readFloatRegBits(int floatReg) - { - return floatRegFile.q[floatReg]; - } - - FloatRegBits - readFloatRegBits(int floatReg, int width) - { - return readFloatRegBits(floatReg); - } - - void - setFloatReg(int floatReg, const FloatReg &val) - { - floatRegFile.d[floatReg] = val; - } - - void - setFloatReg(int floatReg, const FloatReg &val, int width) - { - setFloatReg(floatReg, val); - } - - void - setFloatRegBits(int floatReg, const FloatRegBits &val) - { - floatRegFile.q[floatReg] = val; - } - - void - setFloatRegBits(int floatReg, const FloatRegBits &val, int width) - { - setFloatRegBits(floatReg, val); - } - - IntReg - readIntReg(int intReg) - { - return intRegFile.readReg(intReg); - } - - void - setIntReg(int intReg, const IntReg &val) - { - intRegFile.setReg(intReg, val); - } - - void serialize(EventManager *em, std::ostream &os); - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); -}; - -static inline int -flattenIntIndex(ThreadContext * tc, int reg) -{ - return reg; -} - -static inline int -flattenFloatIndex(ThreadContext * tc, int reg) -{ - return reg; -} - -void copyRegs(ThreadContext *src, ThreadContext *dest); - -void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_REGFILE_HH__ diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh new file mode 100644 index 000000000..ec36ff751 --- /dev/null +++ b/src/arch/alpha/registers.hh @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_ALPHA_REGISTERS_HH__ +#define __ARCH_ALPHA_REGISTERS_HH__ + +#include "arch/alpha/ipr.hh" +#include "arch/alpha/max_inst_regs.hh" +#include "base/types.hh" + +namespace AlphaISA { + +using AlphaISAInst::MaxInstSrcRegs; +using AlphaISAInst::MaxInstDestRegs; + +typedef uint8_t RegIndex; +typedef uint64_t IntReg; + +// floating point register file entry type +typedef double FloatReg; +typedef uint64_t FloatRegBits; + +// control register file contents +typedef uint64_t MiscReg; + +union AnyReg +{ + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; +}; + +enum MiscRegIndex +{ + MISCREG_FPCR = NumInternalProcRegs, + MISCREG_UNIQ, + MISCREG_LOCKFLAG, + MISCREG_LOCKADDR, + MISCREG_INTR +}; + +// semantically meaningful register indices +const RegIndex ZeroReg = 31; // architecturally meaningful +// the rest of these depend on the ABI +const RegIndex StackPointerReg = 30; +const RegIndex GlobalPointerReg = 29; +const RegIndex ProcedureValueReg = 27; +const RegIndex ReturnAddressReg = 26; +const RegIndex ReturnValueReg = 0; +const RegIndex FramePointerReg = 15; + +const RegIndex SyscallNumReg = 0; +const RegIndex FirstArgumentReg = 16; +const RegIndex SyscallPseudoReturnReg = 20; +const RegIndex SyscallSuccessReg = 19; + +const int NumIntArchRegs = 32; +const int NumPALShadowRegs = 8; +const int NumFloatArchRegs = 32; +// @todo: Figure out what this number really should be. +const int NumMiscArchRegs = 77; + +const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; +const int NumFloatRegs = NumFloatArchRegs; +const int NumMiscRegs = NumMiscArchRegs; + +const int TotalNumRegs = + NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs; + +const int TotalDataRegs = NumIntRegs + NumFloatRegs; + +// These enumerate all the registers for dependence tracking. +enum DependenceTags { + // 0..31 are the integer regs 0..31 + // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) + FP_Base_DepTag = 40, + Ctrl_Base_DepTag = 72 +}; + +} // namespace AlphaISA + +#endif // __ARCH_ALPHA_REGFILE_HH__ diff --git a/src/arch/alpha/intregfile.cc b/src/arch/alpha/regredir.cc index 8f692f856..991138f11 100644 --- a/src/arch/alpha/intregfile.cc +++ b/src/arch/alpha/regredir.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2003-2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,11 +30,8 @@ * Kevin Lim */ -#include <cstring> - -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/intregfile.hh" -#include "sim/serialize.hh" +#include "arch/alpha/regredir.hh" +#include "config/full_system.hh" namespace AlphaISA { @@ -52,23 +49,4 @@ const int reg_redir[NumIntRegs] = { /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 }; #endif -void -IntRegFile::clear() -{ - std::memset(regs, 0, sizeof(regs)); -} - -void -IntRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumIntRegs); -} - -void -IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumIntRegs); -} - } // namespace AlphaISA - diff --git a/src/arch/mips/regfile.hh b/src/arch/alpha/regredir.hh index 29586a652..6e12be41f 100644 --- a/src/arch/mips/regfile.hh +++ b/src/arch/alpha/regredir.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2003-2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,9 +28,16 @@ * Authors: Gabe Black */ -#ifndef __ARCH_MIPS_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_HH__ +#ifndef __ARCH_ALPHA_REGREDIR_HH__ +#define __ARCH_ALPHA_REGREDIR_HH__ -#include "arch/mips/regfile/regfile.hh" +#include "arch/alpha/registers.hh" -#endif +namespace AlphaISA { + +// redirected register map, really only used for the full system case. +extern const int reg_redir[NumIntRegs]; + +} // namespace AlphaISA + +#endif // __ARCH_ALPHA_REGREDIR_HH__ diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index c47293b98..5391d2056 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -128,6 +128,7 @@ #include "arch/alpha/kgdb.h" #include "arch/alpha/utility.hh" +#include "arch/alpha/regredir.hh" #include "arch/alpha/remote_gdb.hh" #include "base/intmath.hh" #include "base/remote_gdb.hh" diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh index d670784c4..0d285c3b2 100644 --- a/src/arch/alpha/types.hh +++ b/src/arch/alpha/types.hh @@ -38,25 +38,9 @@ namespace AlphaISA { typedef uint32_t MachInst; typedef uint64_t ExtMachInst; -typedef uint8_t RegIndex; -typedef uint64_t IntReg; typedef uint64_t LargestRead; -// floating point register file entry type -typedef double FloatReg; -typedef uint64_t FloatRegBits; - -// control register file contents -typedef uint64_t MiscReg; - -union AnyReg -{ - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; -}; - enum annotes { ANNOTE_NONE = 0, diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc index 763da0d4f..0d865e520 100644 --- a/src/arch/alpha/utility.cc +++ b/src/arch/alpha/utility.cc @@ -29,6 +29,7 @@ * Ali Saidi */ +#include "arch/alpha/ev5.hh" #include "arch/alpha/utility.hh" #if FULL_SYSTEM @@ -61,5 +62,39 @@ getArgument(ThreadContext *tc, int number, bool fp) #endif } +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + // First loop through the integer registers. + for (int i = 0; i < NumIntRegs; ++i) + dest->setIntReg(i, src->readIntReg(i)); + + // Then loop through the floating point registers. + for (int i = 0; i < NumFloatRegs; ++i) + dest->setFloatRegBits(i, src->readFloatRegBits(i)); + + // Copy misc. registers + copyMiscRegs(src, dest); + + // Lastly copy PC/NPC + dest->setPC(src->readPC()); + dest->setNextPC(src->readNextPC()); +} + +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + dest->setMiscRegNoEffect(MISCREG_FPCR, + src->readMiscRegNoEffect(MISCREG_FPCR)); + dest->setMiscRegNoEffect(MISCREG_UNIQ, + src->readMiscRegNoEffect(MISCREG_UNIQ)); + dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, + src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); + dest->setMiscRegNoEffect(MISCREG_LOCKADDR, + src->readMiscRegNoEffect(MISCREG_LOCKADDR)); + + copyIprs(src, dest); +} + } // namespace AlphaISA diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index 76c6c5726..0b994d324 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -34,7 +34,7 @@ #include "arch/alpha/types.hh" #include "arch/alpha/isa_traits.hh" -#include "arch/alpha/regfile.hh" +#include "arch/alpha/registers.hh" #include "base/misc.hh" #include "config/full_system.hh" #include "cpu/thread_context.hh" @@ -111,10 +111,6 @@ makeRegisterCopy(int dest, int src) return 0; } -// Machine operations -void saveMachineReg(AnyReg &savereg, const RegFile ®_file, int regnum); -void restoreMachineReg(RegFile ®s, const AnyReg ®, int regnum); - /** * Function to insure ISA semantics about 0 registers. * @param tc The thread context. @@ -163,6 +159,10 @@ template <class TC> void processInterrupts(TC *tc); #endif +void copyRegs(ThreadContext *src, ThreadContext *dest); + +void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + } // namespace AlphaISA #endif // __ARCH_ALPHA_UTILITY_HH__ diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 60a5ca3b0..519435489 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -40,7 +40,6 @@ if env['TARGET_ISA'] == 'arm': Source('insts/pred_inst.cc') Source('insts/static_inst.cc') Source('pagetable.cc') - Source('regfile/regfile.cc') Source('tlb.cc') Source('vtophys.cc') diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index b79c09174..3d882c97f 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -433,7 +433,6 @@ void InterruptFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(Arm,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; @@ -469,7 +468,6 @@ void ReservedInstructionFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(Arm,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase); // Offset 0x180 - General Exception Vector diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh index cfc2075a1..541c9e3f5 100644 --- a/src/arch/arm/insts/macromem.hh +++ b/src/arch/arm/insts/macromem.hh @@ -47,6 +47,39 @@ number_of_ones(int32_t val) } /** + * Microops of the form IntRegA = IntRegB op Imm + */ +class MicroIntOp : public PredOp +{ + protected: + RegIndex ura, urb; + uint8_t imm; + + MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, + RegIndex _ura, RegIndex _urb, uint8_t _imm) + : PredOp(mnem, machInst, __opClass), + ura(_ura), urb(_urb), imm(_imm) + { + } +}; + +/** + * Memory microops which use IntReg + Imm addressing + */ +class MicroMemOp : public MicroIntOp +{ + protected: + unsigned memAccessFlags; + + MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, + RegIndex _ura, RegIndex _urb, uint8_t _imm) + : MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm), + memAccessFlags(0) + { + } +}; + +/** * Arm Macro Memory operations like LDM/STM */ class ArmMacroMemoryOp : public PredMacroOp @@ -54,10 +87,6 @@ class ArmMacroMemoryOp : public PredMacroOp protected: /// Memory request flags. See mem_req_base.hh. unsigned memAccessFlags; - /// Pointer to EAComp object. - const StaticInstPtr eaCompPtr; - /// Pointer to MemAcc object. - const StaticInstPtr memAccPtr; uint32_t reglist; uint32_t ones; @@ -69,12 +98,9 @@ class ArmMacroMemoryOp : public PredMacroOp loadop; ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, - StaticInstPtr _eaCompPtr = nullStaticInstPtr, - StaticInstPtr _memAccPtr = nullStaticInstPtr) + OpClass __opClass) : PredMacroOp(mnem, _machInst, __opClass), memAccessFlags(0), - eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), reglist(machInst.regList), ones(0), puswl(machInst.puswl), prepost(machInst.puswl.prepost), diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index 7909330aa..afbf05e44 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -37,14 +37,17 @@ Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - return ss.str(); -} - -std::string -MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const -{ - std::stringstream ss; - printMnemonic(ss); + printReg(ss, machInst.rd); + ss << ", ["; + printReg(ss, machInst.rn); + ss << ", "; + if (machInst.puswl.prepost == 1) + printOffset(ss); + ss << "]"; + if (machInst.puswl.prepost == 0) + printOffset(ss); + else if (machInst.puswl.writeback) + ss << "!"; return ss.str(); } } diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh index 80f966e9c..bf0aa1c92 100644 --- a/src/arch/arm/insts/mem.hh +++ b/src/arch/arm/insts/mem.hh @@ -42,10 +42,6 @@ class Memory : public PredOp /// Memory request flags. See mem_req_base.hh. unsigned memAccessFlags; - /// Pointer to EAComp object. - const StaticInstPtr eaCompPtr; - /// Pointer to MemAcc object. - const StaticInstPtr memAccPtr; /// Displacement for EA calculation (signed). int32_t disp; @@ -56,53 +52,88 @@ class Memory : public PredOp shift; /// Constructor - Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, - StaticInstPtr _eaCompPtr = nullStaticInstPtr, - StaticInstPtr _memAccPtr = nullStaticInstPtr) + Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : PredOp(mnem, _machInst, __opClass), memAccessFlags(0), - eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), disp(machInst.immed11_0), disp8(machInst.immed7_0 << 2), up(machInst.puswl.up), hilo((machInst.immedHi11_8 << 4) | machInst.immedLo3_0), shift_size(machInst.shiftSize), shift(machInst.shift) { - // When Up is not set, then we must subtract by the displacement - if (!up) - { - disp = -disp; - disp8 = -disp8; - hilo = -hilo; - } } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - public: + virtual void + printOffset(std::ostream &os) const + {} +}; - const StaticInstPtr &eaCompInst() const { return eaCompPtr; } - const StaticInstPtr &memAccInst() const { return memAccPtr; } +class MemoryDisp : public Memory +{ + protected: + /// Constructor + MemoryDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) + : Memory(mnem, _machInst, __opClass) + { + } + + void + printOffset(std::ostream &os) const + { + ccprintf(os, "#%#x", (machInst.puswl.up ? disp : -disp)); + } }; - /** - * Base class for a few miscellaneous memory-format insts - * that don't interpret the disp field - */ -class MemoryNoDisp : public Memory +class MemoryHilo : public Memory { protected: /// Constructor - MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, - StaticInstPtr _eaCompPtr = nullStaticInstPtr, - StaticInstPtr _memAccPtr = nullStaticInstPtr) - : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr) + MemoryHilo(const char *mnem, ExtMachInst _machInst, OpClass __opClass) + : Memory(mnem, _machInst, __opClass) { } - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + void + printOffset(std::ostream &os) const + { + ccprintf(os, "#%#x", (machInst.puswl.up ? hilo : -hilo)); + } +}; + +class MemoryShift : public Memory +{ + protected: + /// Constructor + MemoryShift(const char *mnem, ExtMachInst _machInst, OpClass __opClass) + : Memory(mnem, _machInst, __opClass) + { + } + + void + printOffset(std::ostream &os) const + { + printShiftOperand(os); + } +}; + +class MemoryReg : public Memory +{ + protected: + /// Constructor + MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass) + : Memory(mnem, _machInst, __opClass) + { + } + + void + printOffset(std::ostream &os) const + { + os << (machInst.puswl.up ? "+ " : "- "); + printReg(os, machInst.rm); + } }; } diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc index 539cfc2d2..f98db1c8e 100644 --- a/src/arch/arm/insts/pred_inst.cc +++ b/src/arch/arm/insts/pred_inst.cc @@ -32,10 +32,18 @@ namespace ArmISA { std::string -PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - printDataInst(ss); + printDataInst(ss, false); + return ss.str(); +} + +std::string +PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printDataInst(ss, true); return ss.str(); } diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh index 38ac69358..6f9bd9dc2 100644 --- a/src/arch/arm/insts/pred_inst.hh +++ b/src/arch/arm/insts/pred_inst.hh @@ -56,8 +56,6 @@ class PredOp : public ArmStaticInst condCode((ConditionCode)(unsigned)machInst.condCode) { } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; /** @@ -65,23 +63,25 @@ class PredOp : public ArmStaticInst */ class PredImmOp : public PredOp { - protected: - - uint32_t imm; - uint32_t rotate; - uint32_t rotated_imm; - uint32_t rotated_carry; - - /// Constructor - PredImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - PredOp(mnem, _machInst, __opClass), - imm(machInst.imm), rotate(machInst.rotate << 1), - rotated_imm(0), rotated_carry(0) - { - rotated_imm = rotate_imm(imm, rotate); - if (rotate != 0) - rotated_carry = (rotated_imm >> 31) & 1; - } + protected: + + uint32_t imm; + uint32_t rotate; + uint32_t rotated_imm; + uint32_t rotated_carry; + + /// Constructor + PredImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + PredOp(mnem, _machInst, __opClass), + imm(machInst.imm), rotate(machInst.rotate << 1), + rotated_imm(0), rotated_carry(0) + { + rotated_imm = rotate_imm(imm, rotate); + if (rotate != 0) + rotated_carry = (rotated_imm >> 31) & 1; + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; /** @@ -89,17 +89,19 @@ class PredImmOp : public PredOp */ class PredIntOp : public PredOp { - protected: + protected: - uint32_t shift_size; - uint32_t shift; + uint32_t shift_size; + uint32_t shift; - /// Constructor - PredIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - PredOp(mnem, _machInst, __opClass), - shift_size(machInst.shiftSize), shift(machInst.shift) - { - } + /// Constructor + PredIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + PredOp(mnem, _machInst, __opClass), + shift_size(machInst.shiftSize), shift(machInst.shift) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; /** @@ -107,36 +109,36 @@ class PredIntOp : public PredOp */ class PredMacroOp : public PredOp { - protected: - - uint32_t numMicroops; - StaticInstPtr * microOps; - - /// Constructor - PredMacroOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - PredOp(mnem, _machInst, __opClass), - numMicroops(0) - { - // We rely on the subclasses of this object to handle the - // initialization of the micro-operations, since they are - // all of variable length - flags[IsMacroop] = true; - } - - ~PredMacroOp() - { - if (numMicroops) - delete [] microOps; - } - - StaticInstPtr - fetchMicroop(MicroPC microPC) - { - assert(microPC < numMicroops); - return microOps[microPC]; - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + protected: + + uint32_t numMicroops; + StaticInstPtr * microOps; + + /// Constructor + PredMacroOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + PredOp(mnem, _machInst, __opClass), + numMicroops(0) + { + // We rely on the subclasses of this object to handle the + // initialization of the micro-operations, since they are + // all of variable length + flags[IsMacroop] = true; + } + + ~PredMacroOp() + { + if (numMicroops) + delete [] microOps; + } + + StaticInstPtr + fetchMicroop(MicroPC microPC) + { + assert(microPC < numMicroops); + return microOps[microPC]; + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; /** @@ -144,12 +146,12 @@ class PredMacroOp : public PredOp */ class PredMicroop : public PredOp { - /// Constructor - PredMicroop(const char *mnem, MachInst _machInst, OpClass __opClass) : - PredOp(mnem, _machInst, __opClass) - { - flags[IsMicroop] = true; - } + /// Constructor + PredMicroop(const char *mnem, MachInst _machInst, OpClass __opClass) : + PredOp(mnem, _machInst, __opClass) + { + flags[IsMicroop] = true; + } }; } diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index f3ad1127b..df2d5de25 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -330,61 +330,52 @@ ArmStaticInst::printMemSymbol(std::ostream &os, void ArmStaticInst::printShiftOperand(std::ostream &os) const { - // Shifter operand - if (bits((uint32_t)machInst, 25)) { - // Immediate form - unsigned rotate = machInst.rotate * 2; - uint32_t imm = machInst.imm; - ccprintf(os, "#%#x", (imm << (32 - rotate)) | (imm >> rotate)); - } else { - // Register form - printReg(os, machInst.rm); + printReg(os, machInst.rm); - bool immShift = (machInst.opcode4 == 0); - bool done = false; - unsigned shiftAmt = (machInst.shiftSize); - ArmShiftType type = (ArmShiftType)(uint32_t)machInst.shift; + bool immShift = (machInst.opcode4 == 0); + bool done = false; + unsigned shiftAmt = (machInst.shiftSize); + ArmShiftType type = (ArmShiftType)(uint32_t)machInst.shift; - if ((type == LSR || type == ASR) && immShift && shiftAmt == 0) - shiftAmt = 32; + if ((type == LSR || type == ASR) && immShift && shiftAmt == 0) + shiftAmt = 32; - switch (type) { - case LSL: - if (immShift && shiftAmt == 0) { - done = true; - break; - } - os << ", LSL"; - break; - case LSR: - os << ", LSR"; - break; - case ASR: - os << ", ASR"; - break; - case ROR: - if (immShift && shiftAmt == 0) { - os << ", RRX"; - done = true; - break; - } - os << ", ROR"; + switch (type) { + case LSL: + if (immShift && shiftAmt == 0) { + done = true; break; - default: - panic("Tried to disassemble unrecognized shift type.\n"); } - if (!done) { - os << " "; - if (immShift) - os << "#" << shiftAmt; - else - printReg(os, machInst.rs); + os << ", LSL"; + break; + case LSR: + os << ", LSR"; + break; + case ASR: + os << ", ASR"; + break; + case ROR: + if (immShift && shiftAmt == 0) { + os << ", RRX"; + done = true; + break; } + os << ", ROR"; + break; + default: + panic("Tried to disassemble unrecognized shift type.\n"); + } + if (!done) { + os << " "; + if (immShift) + os << "#" << shiftAmt; + else + printReg(os, machInst.rs); } } void -ArmStaticInst::printDataInst(std::ostream &os) const +ArmStaticInst::printDataInst(std::ostream &os, bool withImm) const { printMnemonic(os, machInst.sField ? "s" : ""); //XXX It would be nice if the decoder figured this all out for us. @@ -409,7 +400,13 @@ ArmStaticInst::printDataInst(std::ostream &os) const if (!firstOp) os << ", "; - printShiftOperand(os); + if (withImm) { + unsigned rotate = machInst.rotate * 2; + uint32_t imm = machInst.imm; + ccprintf(os, "#%#x", (imm << (32 - rotate)) | (imm >> rotate)); + } else { + printShiftOperand(os); + } } std::string diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index 22b59791c..c963c1827 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -71,7 +71,7 @@ class ArmStaticInst : public StaticInst void printShiftOperand(std::ostream &os) const; - void printDataInst(std::ostream &os) const; + void printDataInst(std::ostream &os, bool withImm) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/isa.hh index f7e5fbd98..39acc9c08 100644 --- a/src/arch/arm/regfile/misc_regfile.hh +++ b/src/arch/arm/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2007-2008 The Florida State University + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -25,60 +25,82 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Stephen Hines + * Authors: Gabe Black */ -#ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__ -#define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__ +#ifndef __ARCH_ARM_ISA_HH__ +#define __ARCH_MRM_ISA_HH__ +#include "arch/arm/registers.hh" #include "arch/arm/types.hh" -#include "sim/faults.hh" class ThreadContext; +class Checkpoint; +class EventManager; namespace ArmISA { - static inline std::string getMiscRegName(RegIndex) + class ISA { - return ""; - } - - class MiscRegFile { - protected: - MiscReg miscRegFile[NumMiscRegs]; + MiscReg miscRegs[NumMiscRegs]; public: void clear() { - // Unknown startup state in misc register file currently + // Unknown startup state currently + } + + MiscReg + readMiscRegNoEffect(int misc_reg) + { + assert(misc_reg < NumMiscRegs); + return miscRegs[misc_reg]; } - void copyMiscRegs(ThreadContext *tc); + MiscReg + readMiscReg(int misc_reg, ThreadContext *tc) + { + assert(misc_reg < NumMiscRegs); + return miscRegs[misc_reg]; + } - MiscReg readRegNoEffect(int misc_reg) + void + setMiscRegNoEffect(int misc_reg, const MiscReg &val) { - return miscRegFile[misc_reg]; + assert(misc_reg < NumMiscRegs); + miscRegs[misc_reg] = val; } - MiscReg readReg(int misc_reg, ThreadContext *tc) + void + setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) { - return miscRegFile[misc_reg]; + assert(misc_reg < NumMiscRegs); + miscRegs[misc_reg] = val; } - void setRegNoEffect(int misc_reg, const MiscReg &val) + int + flattenIntIndex(int reg) { - miscRegFile[misc_reg] = val; + return reg; } - void setReg(int misc_reg, const MiscReg &val, - ThreadContext *tc) + int + flattenFloatIndex(int reg) { - miscRegFile[misc_reg] = val; + return reg; } - friend class RegFile; + void serialize(std::ostream &os) + {} + void unserialize(Checkpoint *cp, const std::string §ion) + {} + + ISA() + { + clear(); + } }; -} // namespace ArmISA +} #endif diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index 623b2415d..76d584858 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -37,47 +37,8 @@ // in the ARM ISA specification document starting with Table B.1 or 3-1 // // -decode COND_CODE default Unknown::unknown() { - 0xf: decode COND_CODE { - 0x0: decode OPCODE { - // Just a simple trick to allow us to specify our new uops here - 0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }}, - 'IsMicroop'); - 0x1: PredImmOp::subi_uop({{ Raddr = Rn - rotated_imm; }}, - 'IsMicroop'); - 0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }}, - {{ EA = Raddr + disp; }}, - inst_flags = [IsMicroop]); - 0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }}, - {{ EA = Raddr + disp; }}, - inst_flags = [IsMicroop]); - 0x4: PredImmOp::addi_rd_uop({{ Rd = Rn + rotated_imm; }}, - 'IsMicroop'); - 0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }}, - 'IsMicroop'); - } - 0x1: decode OPCODE { - 0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }}, - 'IsMicroop'); - 0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff; - Rlo = Fd.ud & 0xffffffff; }}, - 'IsMicroop'); - 0x2: ArmLoadMemory::ldhi_uop({{ Rhi = Mem; }}, - {{ EA = Rn + disp; }}, - inst_flags = [IsMicroop]); - 0x3: ArmLoadMemory::ldlo_uop({{ Rlo = Mem; }}, - {{ EA = Rn + disp; }}, - inst_flags = [IsMicroop]); - 0x4: ArmStoreMemory::sthi_uop({{ Mem = Rhi; }}, - {{ EA = Rn + disp; }}, - inst_flags = [IsMicroop]); - 0x5: ArmStoreMemory::stlo_uop({{ Mem = Rlo; }}, - {{ EA = Rn + disp; }}, - inst_flags = [IsMicroop]); - } - default: Unknown::unknown(); // TODO: Ignore other NV space for now - } -default: decode ENCODING { + +decode ENCODING default Unknown::unknown() { format DataOp { 0x0: decode SEVEN_AND_FOUR { 1: decode MISC_OPCODE { @@ -112,145 +73,15 @@ format DataOp { 0x19: WarnUnimpl::ldrex(); } } - 0xb: decode PUBWL { - format ArmStoreMemory { - 0x0: strh_({{ Mem.uh = Rd; - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x4: strh_i({{ Mem.uh = Rd; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x8: strh_u({{ Mem.uh = Rd; - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0xc: strh_ui({{ Mem.uh = Rd; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x10: strh_p({{ Mem.uh = Rd; }}, - {{ EA = Rn - Rm; }}); - 0x12: strh_pw({{ Mem.uh = Rd; - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x14: strh_pi({{ Mem.uh = Rd.uh; }}, - {{ EA = Rn + hilo; }}); - 0x16: strh_piw({{ Mem.uh = Rd; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x18: strh_pu({{ Mem.uh = Rd; }}, - {{ EA = Rn + Rm; }}); - 0x1a: strh_puw({{ Mem.uh = Rd; - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1c: strh_pui({{ Mem.uh = Rd; }}, - {{ EA = Rn + hilo; }}); - 0x1e: strh_puiw({{ Mem.uh = Rd; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - } - format ArmLoadMemory { - 0x1: ldrh_l({{ Rd = Mem.uh; - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x5: ldrh_il({{ Rd = Mem.uh; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x9: ldrh_ul({{ Rd = Mem.uh; - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0xd: ldrh_uil({{ Rd = Mem.uh; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x11: ldrh_pl({{ Rd = Mem.uh; }}, - {{ EA = Rn - Rm; }}); - 0x13: ldrh_pwl({{ Rd = Mem.uh; - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x15: ldrh_pil({{ Rd = Mem.uh; }}, - {{ EA = Rn + hilo; }}); - 0x17: ldrh_piwl({{ Rd = Mem.uh; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x19: ldrh_pul({{ Rd = Mem.uh; }}, - {{ EA = Rn + Rm; }}); - 0x1b: ldrh_puwl({{ Rd = Mem.uh; - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1d: ldrh_puil({{ Rd = Mem.uh; }}, - {{ EA = Rn + hilo; }}); - 0x1f: ldrh_puiwl({{ Rd = Mem.uh; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - } - } - format ArmLoadMemory { - 0xd: decode PUBWL { - 0x1: ldrsb_l({{ Rd = Mem.sb; - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x5: ldrsb_il({{ Rd = Mem.sb; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x9: ldrsb_ul({{ Rd = Mem.sb; - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0xd: ldrsb_uil({{ Rd = Mem.sb; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x11: ldrsb_pl({{ Rd = Mem.sb; }}, - {{ EA = Rn - Rm; }}); - 0x13: ldrsb_pwl({{ Rd = Mem.sb; - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x15: ldrsb_pil({{ Rd = Mem.sb; }}, - {{ EA = Rn + hilo; }}); - 0x17: ldrsb_piwl({{ Rd = Mem.sb; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x19: ldrsb_pul({{ Rd = Mem.sb; }}, - {{ EA = Rn + Rm; }}); - 0x1b: ldrsb_puwl({{ Rd = Mem.sb; - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1d: ldrsb_puil({{ Rd = Mem.sb; }}, - {{ EA = Rn + hilo; }}); - 0x1f: ldrsb_puiwl({{ Rd = Mem.sb; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - } - 0xf: decode PUBWL { - 0x1: ldrsh_l({{ Rd = Mem.sh; - Rn = Rn - Rm; }}, - {{ EA = Rn; }}); - 0x5: ldrsh_il({{ Rd = Mem.sh; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x9: ldrsh_ul({{ Rd = Mem.sh; - Rn = Rn + Rm; }}, - {{ EA = Rn; }}); - 0xd: ldrsh_uil({{ Rd = Mem.sh; - Rn = Rn + hilo; }}, - {{ EA = Rn; }}); - 0x11: ldrsh_pl({{ Rd = Mem.sh; }}, - {{ EA = Rn - Rm; }}); - 0x13: ldrsh_pwl({{ Rd = Mem.sh; - Rn = Rn - Rm; }}, - {{ EA = Rn - Rm; }}); - 0x15: ldrsh_pil({{ Rd = Mem.sh; }}, - {{ EA = Rn + hilo; }}); - 0x17: ldrsh_piwl({{ Rd = Mem.sh; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - 0x19: ldrsh_pul({{ Rd = Mem.sh; }}, - {{ EA = Rn + Rm; }}); - 0x1b: ldrsh_puwl({{ Rd = Mem.sh; - Rn = Rn + Rm; }}, - {{ EA = Rn + Rm; }}); - 0x1d: ldrsh_puil({{ Rd = Mem.sh; }}, - {{ EA = Rn + hilo; }}); - 0x1f: ldrsh_puiwl({{ Rd = Mem.sh; - Rn = Rn + hilo; }}, - {{ EA = Rn + hilo; }}); - } + format AddrMode3 { + 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }}, + load, {{ Rd = Mem.uh; }}); + 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0); + Rdo = bits(Mem.ud, 63, 32); }}, + load, {{ Rd = Mem.sb; }}); + 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) | + (Rdo.ud << 32); }}, + load, {{ Rd = Mem.sh; }}); } } 0: decode IS_MISC { @@ -355,107 +186,9 @@ format DataOp { 0xb: WarnUnimpl::mrs_i_spsr(); } } - 0x2: decode PUBWL { - // CAREFUL: - // Can always do EA + disp, since we negate disp using the UP flag - // Post-indexed variants - 0x00,0x08: ArmStoreMemory::str_({{ Mem = Rd; - Rn = Rn + disp; }}, - {{ EA = Rn; }}); - 0x01,0x09: ArmLoadMemory::ldr_l({{ Rn = Rn + disp; - Rd = Mem; }}, - {{ EA = Rn; }}); - 0x04,0x0c: ArmStoreMemory::strb_b({{ Mem.ub = Rd.ub; - Rn = Rn + disp; }}, - {{ EA = Rn; }}); - 0x05,0x0d: ArmLoadMemory::ldrb_bl({{ Rn = Rn + disp; - Rd.ub = Mem.ub; }}, - {{ EA = Rn; }}); - // Pre-indexed variants - 0x10,0x18: ArmStoreMemory::str_p({{ Mem = Rd; }}); - 0x11,0x19: ArmLoadMemory::ldr_pl({{ Rd = Mem; }}); - 0x12,0x1a: ArmStoreMemory::str_pw({{ Mem = Rd; - Rn = Rn + disp; }}); - 0x13,0x1b: ArmLoadMemory::ldr_pwl({{ Rn = Rn + disp; - Rd = Mem; }}); - 0x14,0x1c: ArmStoreMemory::strb_pb({{ Mem.ub = Rd.ub; }}); - 0x15,0x1d: ArmLoadMemory::ldrb_pbl({{ Rd.ub = Mem.ub; }}); - 0x16,0x1e: ArmStoreMemory::strb_pbw({{ Mem.ub = Rd.ub; - Rn = Rn + disp; }}); - 0x17,0x1f: ArmLoadMemory::ldrb_pbwl({{ Rn = Rn + disp; - Rd.ub = Mem.ub; }}); - } + 0x2: AddrMode2::addrMode2(Disp, disp); 0x3: decode OPCODE_4 { - 0: decode PUBWL { - format ArmStoreMemory { - 0x00, 0x02: strr_({{ Mem = Rd; - Rn = Rn - Rm_Imm; }}, - {{ EA = Rn; }}); - 0x04, 0x06: strr_b({{ Mem = Rd.ub; - Rn = Rn - Rm_Imm; }}, - {{ EA = Rn; }}); - 0x08, 0x0a: strr_u({{ Mem = Rd; - Rn = Rn + Rm_Imm; }}, - {{ EA = Rn; }}); - 0x0c, 0x0e: strr_ub({{ Mem.ub = Rd.ub; - Rn = Rn + Rm_Imm; }}, - {{ EA = Rn; }}); - 0x10: strr_p({{ Mem = Rd; }}, - {{ EA = Rn - Rm_Imm; }}); - 0x12: strr_pw({{ Mem = Rd; - Rn = Rn - Rm_Imm; }}, - {{ EA = Rn - Rm_Imm; }}); - 0x14: strr_pb({{ Mem.ub = Rd.ub; }}, - {{ EA = Rn - Rm_Imm; }}); - 0x16: strr_pbw({{ Mem.ub = Rd.ub; - Rn = Rn - Rm_Imm; }}, - {{ EA = Rn - Rm_Imm; }}); - 0x18: strr_pu({{ Mem = Rd; }}, - {{ EA = Rn + Rm_Imm; }}); - 0x1a: strr_puw({{ Mem = Rd; - Rn = Rn + Rm_Imm; }}, - {{ EA = Rn + Rm_Imm; }}); - 0x1c: strr_pub({{ Mem.ub = Rd; }}, - {{ EA = Rn + Rm_Imm; }}); - 0x1e: strr_pubw({{ Mem.ub = Rd; - Rn = Rn + Rm_Imm; }}, - {{ EA = Rn + Rm_Imm; }}); - } - format ArmLoadMemory { - 0x01,0x03: ldrr_l({{ Rd = Mem; - Rn = Rn - Rm_Imm; }}, - {{ EA = Rn; }}); - 0x05,0x07: ldrr_bl({{ Rd = Mem.ub; - Rn = Rn - Rm_Imm; }}, - {{ EA = Rn; }}); - 0x09,0x0b: ldrr_ul({{ Rd = Mem; - Rn = Rn + Rm_Imm; }}, - {{ EA = Rn; }}); - 0x0d,0x0f: ldrr_ubl({{ Rd = Mem.ub; - Rn = Rn + Rm_Imm; }}, - {{ EA = Rn; }}); - 0x11: ldrr_pl({{ Rd = Mem; }}, - {{ EA = Rn - Rm_Imm; }}); - 0x13: ldrr_pwl({{ Rd = Mem; - Rn = Rn - Rm_Imm; }}, - {{ EA = Rn - Rm_Imm; }}); - 0x15: ldrr_pbl({{ Rd = Mem.ub; }}, - {{ EA = Rn - Rm_Imm; }}); - 0x17: ldrr_pbwl({{ Rd = Mem.ub; - Rn = Rn - Rm_Imm; }}, - {{ EA = Rn - Rm_Imm; }}); - 0x19: ldrr_pul({{ Rd = Mem; }}, - {{ EA = Rn + Rm_Imm; }}); - 0x1b: ldrr_puwl({{ Rd = Mem; - Rn = Rn + Rm_Imm; }}, - {{ EA = Rn + Rm_Imm; }}); - 0x1d: ldrr_publ({{ Rd = Mem.ub; }}, - {{ EA = Rn + Rm_Imm; }}); - 0x1f: ldrr_pubwl({{ Rd = Mem.ub; - Rn = Rn + Rm_Imm; }}, - {{ EA = Rn + Rm_Imm; }}); - } - } + 0: AddrMode2::addrMode2(Shift, Rm_Imm); 1: decode MEDIA_OPCODE { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 0x8: decode MISC_OPCODE { @@ -696,5 +429,4 @@ format DataOp { } } } -} diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa index df52f9413..355a67ea9 100644 --- a/src/arch/arm/isa/formats/macromem.isa +++ b/src/arch/arm/isa/formats/macromem.isa @@ -27,6 +27,133 @@ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: Stephen Hines +// Gabe Black + +//////////////////////////////////////////////////////////////////// +// +// Common microop templates +// + +def template MicroConstructor {{ + inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + RegIndex _ura, + RegIndex _urb, + uint8_t _imm) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _ura, _urb, _imm) + { + %(constructor)s; + } +}}; + +//////////////////////////////////////////////////////////////////// +// +// Load/store microops +// + +def template MicroMemDeclare {{ + class %(class_name)s : public %(base_class)s + { + public: + %(class_name)s(ExtMachInst machInst, + RegIndex _ura, RegIndex _urb, + uint8_t _imm); + %(BasicExecDeclare)s + %(InitiateAccDeclare)s + %(CompleteAccDeclare)s + }; +}}; + +let {{ + microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', + 'MicroMemOp', + {'memacc_code': 'Ra = Mem;', + 'ea_code': 'EA = Rb + (UP ? imm : -imm);', + 'predicate_test': predicateTest}, + ['IsMicroop']) + + microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', + 'MicroMemOp', + {'memacc_code': 'Mem = Ra;', + 'ea_code': 'EA = Rb + (UP ? imm : -imm);', + 'predicate_test': predicateTest}, + ['IsMicroop']) + + header_output = MicroMemDeclare.subst(microLdrUopIop) + \ + MicroMemDeclare.subst(microStrUopIop) + decoder_output = MicroConstructor.subst(microLdrUopIop) + \ + MicroConstructor.subst(microStrUopIop) + exec_output = LoadExecute.subst(microLdrUopIop) + \ + StoreExecute.subst(microStrUopIop) + \ + LoadInitiateAcc.subst(microLdrUopIop) + \ + StoreInitiateAcc.subst(microStrUopIop) + \ + LoadCompleteAcc.subst(microLdrUopIop) + \ + StoreCompleteAcc.subst(microStrUopIop) +}}; + +//////////////////////////////////////////////////////////////////// +// +// Integer = Integer op Immediate microops +// + +def template MicroIntDeclare {{ + class %(class_name)s : public %(base_class)s + { + public: + %(class_name)s(ExtMachInst machInst, + RegIndex _ura, RegIndex _urb, + uint8_t _imm); + %(BasicExecDeclare)s + }; +}}; + +let {{ + microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', + 'MicroIntOp', + {'code': 'Ra = Rb + imm;', + 'predicate_test': predicateTest}, + ['IsMicroop']) + + microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', + 'MicroIntOp', + {'code': 'Ra = Rb - imm;', + 'predicate_test': predicateTest}, + ['IsMicroop']) + + header_output = MicroIntDeclare.subst(microAddiUopIop) + \ + MicroIntDeclare.subst(microSubiUopIop) + decoder_output = MicroConstructor.subst(microAddiUopIop) + \ + MicroConstructor.subst(microSubiUopIop) + exec_output = PredOpExecute.subst(microAddiUopIop) + \ + PredOpExecute.subst(microSubiUopIop) +}}; + +//////////////////////////////////////////////////////////////////// +// +// Moving to/from double floating point registers +// + +let {{ + microMvtdUopIop = InstObjParams('mvtd_uop', 'MicroMvtdUop', + 'PredOp', + {'code': 'Fd.ud = (Rhi.ud << 32) | Rlo;', + 'predicate_test': predicateTest}, + ['IsMicroop']) + + microMvfdUopIop = InstObjParams('mvfd_uop', 'MicroMvfdUop', + 'PredOp', + {'code': '''Rhi = bits(Fd.ud, 63, 32); + Rlo = bits(Fd.ud, 31, 0);''', + 'predicate_test': predicateTest}, + ['IsMicroop']) + + header_output = BasicDeclare.subst(microMvtdUopIop) + \ + BasicDeclare.subst(microMvfdUopIop) + decoder_output = BasicConstructor.subst(microMvtdUopIop) + \ + BasicConstructor.subst(microMvfdUopIop) + exec_output = PredOpExecute.subst(microMvtdUopIop) + \ + PredOpExecute.subst(microMvfdUopIop) +}}; //////////////////////////////////////////////////////////////////// // @@ -52,9 +179,7 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) { %(constructor)s; uint32_t regs_to_handle = reglist; - uint32_t j = 0, - start_addr = 0, - end_addr = 0; + uint32_t start_addr = 0; switch (puswl) { @@ -63,28 +188,24 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) case 0x02: // W stmda_w case 0x03: // WL ldmda_wl start_addr = (ones << 2) - 4; - end_addr = 0; break; case 0x08: // U stmia_u case 0x09: // U L ldmia_ul case 0x0a: // U W stmia case 0x0b: // U WL ldmia start_addr = 0; - end_addr = (ones << 2) - 4; break; case 0x10: // P stmdb case 0x11: // P L ldmdb case 0x12: // P W stmdb case 0x13: // P WL ldmdb start_addr = (ones << 2); // U-bit is already 0 for subtract - end_addr = 4; // negative 4 break; case 0x18: // PU stmib case 0x19: // PU L ldmib case 0x1a: // PU W stmib case 0x1b: // PU WL ldmib start_addr = 4; - end_addr = (ones << 2) + 4; break; default: panic("Unhandled Load/Store Multiple Instruction, " @@ -92,20 +213,21 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) break; } - //TODO - Add addi_uop/subi_uop here to create starting addresses - //Just using addi with 0 offset makes a "copy" of Rn for our use - uint32_t newMachInst = 0; - newMachInst = machInst & 0xffff0000; - microOps[0] = new Addi_uop(newMachInst); + // Add 0 to Rn and stick it in Raddr (register 17). + // This is equivalent to a move. + microOps[0] = new MicroAddiUop(machInst, 17, RN, 0); - for (int i = 1; i < ones+1; i++) - { + unsigned j = 0; + for (int i = 1; i < ones+1; i++) { // Get next available bit for transfer while (! ( regs_to_handle & (1<<j))) j++; regs_to_handle &= ~(1<<j); - microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr); + if (loadop) + microOps[i] = new MicroLdrUop(machInst, j, 17, start_addr); + else + microOps[i] = new MicroStrUop(machInst, j, 17, start_addr); if (up) start_addr += 4; @@ -113,33 +235,13 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) start_addr -= 4; } - /* TODO: Take a look at how these 2 values should meet together - if (start_addr != (end_addr - 4)) - { - fprintf(stderr, "start_addr: %d\n", start_addr); - fprintf(stderr, "end_addr: %d\n", end_addr); - panic("start_addr does not meet end_addr"); - } - */ - - if (writeback) - { - uint32_t newMachInst = machInst & 0xf0000000; - uint32_t rn = (machInst >> 16) & 0x0f; - // 3322 2222 2222 1111 1111 11 - // 1098 7654 3210 9876 5432 1098 7654 3210 - // COND 0010 0100 [RN] [RD] 0000 [ IMM ] - // sub rn, rn, imm - newMachInst |= 0x02400000; - newMachInst |= ((rn << 16) | (rn << 12)); - newMachInst |= (ones << 2); - if (up) - { - microOps[numMicroops-1] = new Addi_rd_uop(newMachInst); - } - else - { - microOps[numMicroops-1] = new Subi_rd_uop(newMachInst); + if (writeback) { + if (up) { + microOps[numMicroops-1] = + new MicroAddiUop(machInst, RN, RN, ones * 4); + } else { + microOps[numMicroops-1] = + new MicroSubiUop(machInst, RN, RN, ones * 4); } } microOps[numMicroops-1]->setLastMicroop(); @@ -182,23 +284,12 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) if (writeback) { - uint32_t newMachInst = machInst & 0xf0000000; - uint32_t rn = (machInst >> 16) & 0x0f; - // 3322 2222 2222 1111 1111 11 - // 1098 7654 3210 9876 5432 1098 7654 3210 - // COND 0010 0100 [RN] [RD] 0000 [ IMM ] - // sub rn, rn, imm - newMachInst |= 0x02400000; - newMachInst |= ((rn << 16) | (rn << 12)); - if (up) - { - newMachInst |= disp8; - microOps[numMicroops-1] = new Addi_rd_uop(newMachInst); - } - else - { - newMachInst |= disp8; - microOps[numMicroops-1] = new Subi_rd_uop(newMachInst); + if (up) { + microOps[numMicroops-1] = + new MicroAddiUop(machInst, RN, RN, disp8); + } else { + microOps[numMicroops-1] = + new MicroSubiUop(machInst, RN, RN, disp8); } } microOps[numMicroops-1]->setLastMicroop(); @@ -221,29 +312,15 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) start_addr = 0; for (int i = 0; i < count; i++) - { emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr); - } - if (writeback) - { - uint32_t newMachInst = machInst & 0xf0000000; - uint32_t rn = (machInst >> 16) & 0x0f; - // 3322 2222 2222 1111 1111 11 - // 1098 7654 3210 9876 5432 1098 7654 3210 - // COND 0010 0100 [RN] [RD] 0000 [ IMM ] - // sub rn, rn, imm - newMachInst |= 0x02400000; - newMachInst |= ((rn << 16) | (rn << 12)); - if (up) - { - newMachInst |= disp8; - microOps[numMicroops-1] = new Addi_rd_uop(newMachInst); - } - else - { - newMachInst |= disp8; - microOps[numMicroops-1] = new Subi_rd_uop(newMachInst); + if (writeback) { + if (up) { + microOps[numMicroops-1] = + new MicroAddiUop(machInst, RN, RN, disp8); + } else { + microOps[numMicroops-1] = + new MicroSubiUop(machInst, RN, RN, disp8); } } microOps[numMicroops-1]->setLastMicroop(); diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index c8ac19c61..0b0a4c9fa 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -39,32 +39,6 @@ def template LoadStoreDeclare {{ */ class %(class_name)s : public %(base_class)s { - protected: - - /** - * "Fake" effective address computation class for "%(mnemonic)s". - */ - class EAComp : public %(base_class)s - { - public: - /// Constructor - EAComp(ExtMachInst machInst); - - %(BasicExecDeclare)s - }; - - /** - * "Fake" memory access instruction class for "%(mnemonic)s". - */ - class MemAcc : public %(base_class)s - { - public: - /// Constructor - MemAcc(ExtMachInst machInst); - - %(BasicExecDeclare)s - }; - public: /// Constructor. @@ -89,87 +63,15 @@ def template CompleteAccDeclare {{ }}; -def template EACompConstructor {{ - inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst) - : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) - { - %(constructor)s; - } -}}; - - -def template MemAccConstructor {{ - inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst) - : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) - { - %(constructor)s; - } -}}; - - def template LoadStoreConstructor {{ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, - new EAComp(machInst), new MemAcc(machInst)) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; } }}; -def template EACompExecute {{ - Fault - %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(op_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (%(predicate_test)s) - { - if (fault == NoFault) { - %(op_wb)s; - xc->setEA(EA); - } - } - - return fault; - } -}}; - -def template LoadMemAccExecute {{ - Fault - %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(op_decl)s; - %(op_rd)s; - EA = xc->getEA(); - - if (%(predicate_test)s) - { - if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); - %(memacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - } - - return fault; - } -}}; - - def template LoadExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const @@ -250,37 +152,6 @@ def template LoadCompleteAcc {{ }}; -def template StoreMemAccExecute {{ - Fault - %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(op_decl)s; - %(op_rd)s; - - if (%(predicate_test)s) - { - EA = xc->getEA(); - - if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, - memAccessFlags, NULL); - if (traceData) { traceData->setData(Mem); } - } - - if (fault == NoFault) { - %(op_wb)s; - } - } - - return fault; - } -}}; - - def template StoreExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const @@ -354,7 +225,8 @@ def template StoreCompleteAcc {{ { Fault fault = NoFault; - %(op_dest_decl)s; + %(op_decl)s; + %(op_rd)s; if (%(predicate_test)s) { @@ -387,71 +259,114 @@ def template StoreCondCompleteAcc {{ } }}; - -def template MiscMemAccExecute {{ - Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(op_decl)s; - %(op_rd)s; - - if (%(predicate_test)s) - { - EA = xc->getEA(); - - if (fault == NoFault) { - %(memacc_code)s; - } - } - - return NoFault; - } -}}; - -def template MiscExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(op_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (%(predicate_test)s) - { - if (fault == NoFault) { - %(memacc_code)s; - } - } - - return NoFault; - } +let {{ + def buildPUBWLCase(p, u, b, w, l): + return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0) + + def buildMode2Inst(p, u, b, w, l, suffix, offset): + mnem = ("str", "ldr")[l] + op = ("-", "+")[u] + offset = op + ArmGenericCodeSubs(offset); + mem = ("Mem", "Mem.ub")[b] + code = ("%s = Rd;", "Rd = %s;")[l] % mem + ea_code = "EA = Rn %s;" % ("", offset)[p] + if p == 0 or w == 1: + code += "Rn = Rn %s;" % offset + if p == 0 and w == 0: + # Here's where we'll tack on a flag to make this a usermode access. + mnem += "t" + type = ("Store", "Load")[l] + newSuffix = "_%s_P%dU%dB%dW%d" % (suffix, p, u, b, w) + if b == 1: + mnem += "b" + return LoadStoreBase(mnem, mnem.capitalize() + newSuffix, + ea_code, code, mem_flags = [], inst_flags = [], + base_class = 'Memory' + suffix, + exec_template_base = type.capitalize()) + + def buildMode3Inst(p, u, i, w, type, code, mnem): + op = ("-", "+")[u] + offset = ("%s Rm", "%s hilo")[i] % op + ea_code = "EA = Rn %s;" % ("", offset)[p] + if p == 0 or w == 1: + code += "Rn = Rn %s;" % offset + newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w) + suffix = ("Reg", "Hilo")[i] + return LoadStoreBase(mnem, mnem.capitalize() + newSuffix, + ea_code, code, mem_flags = [], inst_flags = [], + base_class = 'Memory' + suffix, + exec_template_base = type.capitalize()) }}; -def template MiscInitiateAcc {{ - Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - panic("Misc instruction does not support split access method!"); - return NoFault; - } +def format AddrMode2(suffix, offset) {{ + header_output = decoder_output = exec_output = "" + decode_block = "switch(PUBWL) {\n" + + # Loop over all the values of p, u, b, w and l and build instructions and + # a decode block for them. + for p in (0, 1): + for u in (0, 1): + for b in (0, 1): + for w in (0, 1): + for l in (0, 1): + (new_header_output, + new_decoder_output, + new_decode_block, + new_exec_output) = buildMode2Inst(p, u, b, w, l, + suffix, offset) + header_output += new_header_output + decoder_output += new_decoder_output + exec_output += new_exec_output + decode_block += ''' + case %#x: + {%s} + break; + ''' % (buildPUBWLCase(p,u,b,w,l), new_decode_block) + decode_block += ''' + default: + return new Unknown(machInst); + break; + }''' }}; - -def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - %(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - panic("Misc instruction does not support split access method!"); - - return NoFault; - } +def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{ + l0Code = ArmGenericCodeSubs(l0Code); + l1Code = ArmGenericCodeSubs(l1Code); + + header_output = decoder_output = exec_output = "" + decode_block = "switch(PUBWL) {\n" + (l0Mnem, l1Mnem) = name.split("_"); + + # Loop over all the values of p, u, i, w and l and build instructions and + # a decode block for them. + for (l, type, code, mnem) in ((0, l0Type, l0Code, l0Mnem), + (1, l1Type, l1Code, l1Mnem)): + for p in (0, 1): + wset = (0, 1) + if (p == 0): + wset = (0,) + for u in (0, 1): + for i in (0, 1): + for w in wset: + (new_header_output, + new_decoder_output, + new_decode_block, + new_exec_output) = buildMode3Inst(p, u, i, w, + type, code, mnem) + header_output += new_header_output + decoder_output += new_decoder_output + exec_output += new_exec_output + decode_block += ''' + case %#x: + {%s} + break; + ''' % (buildPUBWLCase(p,u,i,w,l), new_decode_block) + + decode_block += ''' + default: + return new Unknown(machInst); + break; + }''' }}; def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }}, diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa index 5caab642c..b5efec568 100644 --- a/src/arch/arm/isa/formats/util.isa +++ b/src/arch/arm/isa/formats/util.isa @@ -35,7 +35,6 @@ def ArmGenericCodeSubs(code): # Substitute in the shifted portion of operations new_code = re.sub(r'Rm_Imm', 'shift_rm_imm(Rm, shift_size, shift, Cpsr<29:>)', code) new_code = re.sub(r'Rm_Rs', 'shift_rm_rs(Rm, Rs, shift, Cpsr<29:>)', new_code) - new_code = re.sub(r'^', 'Cpsr = Cpsr;', new_code) return new_code def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, @@ -45,31 +44,11 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, mem_flags = makeList(mem_flags) inst_flags = makeList(inst_flags) - # add hook to get effective addresses into execution trace output. - ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' - - # Some CPU models execute the memory operation as an atomic unit, - # while others want to separate them into an effective address - # computation and a memory access operation. As a result, we need - # to generate three StaticInst objects. Note that the latter two - # are nested inside the larger "atomic" one. - - # Generate InstObjParams for each of the three objects. Note that - # they differ only in the set of code objects contained (which in - # turn affects the object's overall operand list). iop = InstObjParams(name, Name, base_class, {'ea_code': ea_code, 'memacc_code': memacc_code, 'predicate_test': predicateTest}, inst_flags) - ea_iop = InstObjParams(name, Name, base_class, - {'ea_code': ea_code, - 'predicate_test': predicateTest}, - inst_flags) - memacc_iop = InstObjParams(name, Name, base_class, - {'memacc_code': memacc_code, - 'predicate_test': predicateTest}, - inst_flags) if mem_flags: s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' @@ -82,20 +61,15 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, # corresponding Store template.. StoreCondInitiateAcc = StoreInitiateAcc - memAccExecTemplate = eval(exec_template_base + 'MemAccExecute') fullExecTemplate = eval(exec_template_base + 'Execute') initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') completeAccTemplate = eval(exec_template_base + 'CompleteAcc') # (header_output, decoder_output, decode_block, exec_output) return (LoadStoreDeclare.subst(iop), - EACompConstructor.subst(ea_iop) - + MemAccConstructor.subst(memacc_iop) - + LoadStoreConstructor.subst(iop), + LoadStoreConstructor.subst(iop), decode_template.subst(iop), - EACompExecute.subst(ea_iop) - + memAccExecTemplate.subst(memacc_iop) - + fullExecTemplate.subst(iop) + fullExecTemplate.subst(iop) + initiateAccTemplate.subst(iop) + completeAccTemplate.subst(iop)) }}; @@ -127,67 +101,25 @@ output decoder {{ return str; } - // Generate the bit pattern for an Ldr_uop or Str_uop; - StaticInstPtr - gen_ldrstr_uop(uint32_t baseinst, int loadop, uint32_t rd, int32_t disp) - { - StaticInstPtr newInst; - uint32_t newMachInst = baseinst & 0xffff0000; - newMachInst |= (rd << 12); - newMachInst |= disp; - if (loadop) - newInst = new Ldr_uop(newMachInst); - else - newInst = new Str_uop(newMachInst); - return newInst; - } - // Emits uops for a double fp move - int - emit_ldfstf_uops(StaticInstPtr* microOps, int index, uint32_t baseinst, int loadop, int up, int32_t disp) + void + emit_ldfstf_uops(StaticInstPtr* microOps, int index, ExtMachInst machInst, + bool loadop, bool up, int32_t disp) { - StaticInstPtr newInst; - uint32_t newMachInst; - if (loadop) { - newMachInst = baseinst & 0xfffff000; - newMachInst |= (disp & 0x0fff); - newInst = new Ldlo_uop(newMachInst); - microOps[index++] = newInst; - - newMachInst = baseinst & 0xfffff000; - if (up) - newMachInst |= ((disp + 4) & 0x0fff); - else - newMachInst |= ((disp - 4) & 0x0fff); - newInst = new Ldhi_uop(newMachInst); - microOps[index++] = newInst; - - newMachInst = baseinst & 0xf000f000; - newInst = new Mvtd_uop(newMachInst); - microOps[index++] = newInst; + microOps[index++] = new MicroLdrUop(machInst, 19, RN, disp); + microOps[index++] = + new MicroLdrUop(machInst, 18, RN, disp + (up ? 4 : -4)); + microOps[index++] = new MicroMvtdUop(machInst); } else { - newMachInst = baseinst & 0xf000f000; - newInst = new Mvfd_uop(newMachInst); - microOps[index++] = newInst; - - newMachInst = baseinst & 0xfffff000; - newMachInst |= (disp & 0x0fff); - newInst = new Stlo_uop(newMachInst); - microOps[index++] = newInst; - - newMachInst = baseinst & 0xfffff000; - if (up) - newMachInst |= ((disp + 4) & 0x0fff); - else - newMachInst |= ((disp - 4) & 0x0fff); - newInst = new Sthi_uop(newMachInst); - microOps[index++] = newInst; + microOps[index++] = new MicroMvfdUop(machInst); + microOps[index++] = new MicroStrUop(machInst, 19, RN, disp); + microOps[index++] = + new MicroStrUop(machInst, 18, RN, disp + (up ? 4 : -4)); } - return 3; } }}; diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index c056d41f2..fa41918c1 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -40,29 +40,48 @@ def operand_types {{ 'df' : ('float', 64) }}; +let {{ + maybePCRead = ''' + ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) : + xc->%(func)s(this, %(op_idx)s)) + ''' + maybePCWrite = ''' + ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) : + xc->%(func)s(this, %(op_idx)s, %(final_val)s)) + ''' +}}; + def operands {{ #General Purpose Integer Reg Operands - 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), - 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2), - 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3), - 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4), + 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), + 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), + 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), + 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), + + #Destination register for load/store double instructions + 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), + 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), + + 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6), + 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7), + 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8), + 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9), - 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5), - 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 5), - 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 6), - 'LR': ('IntReg', 'uw', '14', 'IsInteger', 6), + #Register fields for microops + 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), + 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), #General Purpose Floating Point Reg Operands - 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1), - 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2), - 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3), + 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), + 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), + 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), #Memory Operand - 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8), + 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), - 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7), - 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7), - 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9), - 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9), + 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40), + 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41), + 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42), + 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43), }}; diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh index 6f5e17497..542174b6b 100644 --- a/src/arch/arm/isa_traits.hh +++ b/src/arch/arm/isa_traits.hh @@ -95,46 +95,6 @@ namespace ArmISA // return a no-op instruction... used for instruction fetch faults const ExtMachInst NoopMachInst = 0x00000000; - // Constants Related to the number of registers - const int NumIntArchRegs = 16; - const int NumIntSpecialRegs = 19; - const int NumFloatArchRegs = 16; - const int NumFloatSpecialRegs = 5; - const int NumControlRegs = 7; - const int NumInternalProcRegs = 0; - - const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; - const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; - const int NumMiscRegs = NumControlRegs; - - const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; - - const int TotalDataRegs = NumIntRegs + NumFloatRegs; - - // Static instruction parameters - const int MaxInstSrcRegs = 5; - const int MaxInstDestRegs = 3; - - // semantically meaningful register indices - const int ReturnValueReg = 0; - const int ReturnValueReg1 = 1; - const int ReturnValueReg2 = 2; - const int ArgumentReg0 = 0; - const int ArgumentReg1 = 1; - const int ArgumentReg2 = 2; - const int ArgumentReg3 = 3; - const int FramePointerReg = 11; - const int StackPointerReg = 13; - const int ReturnAddressReg = 14; - const int PCReg = 15; - - const int ZeroReg = NumIntArchRegs; - const int AddrReg = ZeroReg + 1; // Used to generate address for uops - - const int SyscallNumReg = ReturnValueReg; - const int SyscallPseudoReturnReg = ReturnValueReg; - const int SyscallSuccessReg = ReturnValueReg; - const int LogVMPageSize = 12; // 4K bytes const int VMPageSize = (1 << LogVMPageSize); @@ -144,10 +104,6 @@ namespace ArmISA const int WordBytes = 4; const int HalfwordBytes = 2; const int ByteBytes = 1; - - // These help enumerate all the registers for dependence tracking. - const int FP_Base_DepTag = NumIntRegs; - const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; }; using namespace ArmISA; diff --git a/src/arch/arm/regfile.hh b/src/arch/arm/regfile.hh deleted file mode 100644 index 91cc67be0..000000000 --- a/src/arch/arm/regfile.hh +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Stephen Hines - */ - -#ifndef __ARCH_ARM_REGFILE_HH__ -#define __ARCH_ARM_REGFILE_HH__ - -#include "arch/arm/regfile/regfile.hh" - -#endif diff --git a/src/arch/arm/regfile/float_regfile.hh b/src/arch/arm/regfile/float_regfile.hh deleted file mode 100644 index 757f5f0df..000000000 --- a/src/arch/arm/regfile/float_regfile.hh +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Stephen Hines - */ - -#ifndef __ARCH_ARM_REGFILE_FLOAT_REGFILE_HH__ -#define __ARCH_ARM_REGFILE_FLOAT_REGFILE_HH__ - -#include "arch/arm/types.hh" -#include "arch/arm/isa_traits.hh" -#include "base/misc.hh" -#include "base/bitfield.hh" -#include "sim/faults.hh" -#include "sim/serialize.hh" - -#include <string> - -class Checkpoint; - -namespace ArmISA -{ - static inline std::string getFloatRegName(RegIndex) - { - return ""; - } - - const uint32_t ARM32_QNAN = 0x7fbfffff; - const uint64_t ARM64_QNAN = ULL(0x7fbfffffffffffff); - - enum FPControlRegNums { - FIR = NumFloatArchRegs, - FCCR, - FEXR, - FENR, - FCSR - }; - - enum FCSRBits { - Inexact = 1, - Underflow, - Overflow, - DivideByZero, - Invalid, - Unimplemented - }; - - enum FCSRFields { - Flag_Field = 1, - Enable_Field = 6, - Cause_Field = 11 - }; - - const int SingleWidth = 32; - const int SingleBytes = SingleWidth / 4; - - const int DoubleWidth = 64; - const int DoubleBytes = DoubleWidth / 4; - - const int QuadWidth = 128; - const int QuadBytes = QuadWidth / 4; - - class FloatRegFile - { - protected: - union { - FloatRegBits qregs[NumFloatRegs]; - FloatRegVal regs[NumFloatRegs]; - }; - - public: - - void clear() - { - bzero(regs, sizeof(regs)); - regs[8] = 0.0; - regs[9] = 1.0; - regs[10] = 2.0; - regs[11] = 3.0; - regs[12] = 4.0; - regs[13] = 5.0; - regs[14] = 0.5; - regs[15] = 10.0; - } - - FloatRegVal readReg(int floatReg, int width) - { - return regs[floatReg]; - } - - FloatRegBits readRegBits(int floatReg, int width) - { - //return qregs[floatReg]; - switch(width) - { - case SingleWidth: - { - union { - float f; - uint32_t i; - } s; - s.f = (float) regs[floatReg]; - return s.i; - } - case DoubleWidth: - { - uint64_t tmp = (qregs[floatReg]<<32|qregs[floatReg]>>32); - return tmp; - } - default: - panic("Attempted to read a %d bit floating point " - "register!", width); - - } - } - - Fault setReg(int floatReg, const FloatRegVal &val, int width) - { - if (floatReg > 7) - panic("Writing to a hard-wired FP register"); - regs[floatReg] = val; - return NoFault; - } - - Fault setRegBits(int floatReg, const FloatRegBits &val, int width) - { - if (floatReg > 7) - panic("Writing to a hard-wired FP register"); - switch(width) - { - case DoubleWidth: - { - uint64_t tmp = (val << 32 | val >> 32); - qregs[floatReg] = tmp; - return NoFault; - } - case SingleWidth: - default: - panic("Attempted to write a %d bit floating point " - "register!", width); - } - } - - void serialize(std::ostream &os) - { - SERIALIZE_ARRAY(regs, NumFloatRegs); - } - - void unserialize(Checkpoint *cp, const std::string §ion) - { - UNSERIALIZE_ARRAY(regs, NumFloatRegs); - } - }; - -} // namespace ArmISA - -#endif diff --git a/src/arch/arm/regfile/int_regfile.hh b/src/arch/arm/regfile/int_regfile.hh deleted file mode 100644 index b22129f33..000000000 --- a/src/arch/arm/regfile/int_regfile.hh +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Stephen Hines - */ - -#ifndef __ARCH_ARM_REGFILE_INT_REGFILE_HH__ -#define __ARCH_ARM_REGFILE_INT_REGFILE_HH__ - -#include "arch/arm/isa_traits.hh" -#include "arch/arm/types.hh" -#include "base/misc.hh" -#include "base/trace.hh" -#include "sim/faults.hh" -#include "sim/serialize.hh" - -class Checkpoint; -class ThreadContext; - -namespace ArmISA -{ - static inline std::string getIntRegName(RegIndex) - { - return ""; - } - - enum MiscIntRegNums { - zero_reg = NumIntArchRegs, - addr_reg, - - rhi, - rlo, - - r8_fiq, /* FIQ mode register bank */ - r9_fiq, - r10_fiq, - r11_fiq, - r12_fiq, - - r13_fiq, /* FIQ mode SP and LR */ - r14_fiq, - - r13_irq, /* IRQ mode SP and LR */ - r14_irq, - - r13_svc, /* SVC mode SP and LR */ - r14_svc, - - r13_undef, /* UNDEF mode SP and LR */ - r14_undef, - - r13_abt, /* ABT mode SP and LR */ - r14_abt - }; - - class IntRegFile - { - protected: - IntReg regs[NumIntRegs]; - - public: - IntReg readReg(int intReg) - { - DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", - intReg, regs[intReg]); - return regs[intReg]; - } - - void clear() - { - bzero(regs, sizeof(regs)); - } - - Fault setReg(int intReg, const IntReg &val) - { - DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", intReg, val); - regs[intReg] = val; - return NoFault; - } - - void serialize(std::ostream &os) - { - SERIALIZE_ARRAY(regs, NumIntRegs); - } - - void unserialize(Checkpoint *cp, const std::string §ion) - { - UNSERIALIZE_ARRAY(regs, NumIntRegs); - } - }; - -} // namespace ArmISA - -#endif diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc deleted file mode 100644 index a4d6e9a4a..000000000 --- a/src/arch/arm/regfile/regfile.cc +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Stephen Hines - */ - -#include "arch/arm/regfile/regfile.hh" -#include "sim/serialize.hh" - -using namespace std; - -namespace ArmISA -{ - -void -copyRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Regs Not Implemented Yet\n"); -} - -void -copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} - -void -MiscRegFile::copyMiscRegs(ThreadContext *tc) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} - -void -RegFile::serialize(EventManager *em, ostream &os) -{ - intRegFile.serialize(os); - //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs); - //SERIALZE_ARRAY(miscRegFile); - //SERIALIZE_SCALAR(miscRegs.fpcr); - //SERIALIZE_SCALAR(miscRegs.lock_flag); - //SERIALIZE_SCALAR(miscRegs.lock_addr); - //SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - -void -RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) -{ - intRegFile.unserialize(cp, section); - //UNSERIALIZE_ARRAY(floatRegFile); - //UNSERIALZE_ARRAY(miscRegFile); - //UNSERIALIZE_SCALAR(miscRegs.fpcr); - //UNSERIALIZE_SCALAR(miscRegs.lock_flag); - //UNSERIALIZE_SCALAR(miscRegs.lock_addr); - //UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); - -} - -} // namespace ArmISA diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh deleted file mode 100644 index 7f4d21353..000000000 --- a/src/arch/arm/regfile/regfile.hh +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Stephen Hines - */ - -#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__ -#define __ARCH_ARM_REGFILE_REGFILE_HH__ - -#include "arch/arm/types.hh" -#include "arch/arm/regfile/int_regfile.hh" -#include "arch/arm/regfile/float_regfile.hh" -#include "arch/arm/regfile/misc_regfile.hh" -#include "sim/faults.hh" - -class Checkpoint; -class EventManager; -class ThreadContext; - -namespace ArmISA -{ - class RegFile - { - protected: - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file - - public: - - void clear() - { - intRegFile.clear(); - floatRegFile.clear(); - miscRegFile.clear(); - } - - MiscReg readMiscRegNoEffect(int miscReg) - { - return miscRegFile.readRegNoEffect(miscReg); - } - - MiscReg readMiscReg(int miscReg, ThreadContext *tc) - { - return miscRegFile.readReg(miscReg, tc); - } - - void setMiscRegNoEffect(int miscReg, const MiscReg &val) - { - miscRegFile.setRegNoEffect(miscReg, val); - } - - void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc) - { - miscRegFile.setReg(miscReg, val, tc); - } - - FloatRegVal readFloatReg(int floatReg) - { - return floatRegFile.readReg(floatReg,SingleWidth); - } - - FloatRegVal readFloatReg(int floatReg, int width) - { - return floatRegFile.readReg(floatReg,width); - } - - FloatRegBits readFloatRegBits(int floatReg) - { - return floatRegFile.readRegBits(floatReg,SingleWidth); - } - - FloatRegBits readFloatRegBits(int floatReg, int width) - { - return floatRegFile.readRegBits(floatReg,width); - } - - void setFloatReg(int floatReg, const FloatRegVal &val) - { - floatRegFile.setReg(floatReg, val, SingleWidth); - } - - void setFloatReg(int floatReg, const FloatRegVal &val, int width) - { - floatRegFile.setReg(floatReg, val, width); - } - - void setFloatRegBits(int floatReg, const FloatRegBits &val) - { - floatRegFile.setRegBits(floatReg, val, SingleWidth); - } - - void setFloatRegBits(int floatReg, const FloatRegBits &val, int width) - { - floatRegFile.setRegBits(floatReg, val, width); - } - - IntReg readIntReg(int intReg) - { - // In the Arm, reading from the PC for a generic instruction yields - // the current PC + 8, due to previous pipeline implementations - if (intReg == PCReg) - return intRegFile.readReg(intReg) + 8; - //return pc + 8; - else - return intRegFile.readReg(intReg); - } - - void setIntReg(int intReg, const IntReg &val) - { - // Have to trap writes to PC so that they update NPC instead - if (intReg == PCReg) - setNextPC(val); - else - intRegFile.setReg(intReg, val); - } - protected: - - Addr pc; // program counter - Addr npc; // next-cycle program counter - Addr nnpc; // next-next-cycle program counter - - public: - Addr readPC() - { - return intRegFile.readReg(PCReg); - //return pc; - } - - void setPC(Addr val) - { - intRegFile.setReg(PCReg, val); - //pc = val; - } - - Addr readNextPC() - { - return npc; - } - - void setNextPC(Addr val) - { - npc = val; - } - - Addr readNextNPC() - { - return npc + sizeof(MachInst); - } - - void setNextNPC(Addr val) - { - //nnpc = val; - } - - void serialize(EventManager *em, std::ostream &os); - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); - - void changeContext(RegContextParam param, RegContextVal val) - { - } - }; - - static inline int flattenIntIndex(ThreadContext * tc, int reg) - { - return reg; - } - - static inline int flattenFloatIndex(ThreadContext * tc, int reg) - { - return reg; - } - - void copyRegs(ThreadContext *src, ThreadContext *dest); - - void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - -} // namespace ArmISA - -#endif diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh new file mode 100644 index 000000000..7f9b6b828 --- /dev/null +++ b/src/arch/arm/registers.hh @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2007-2008 The Florida State University + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Stephen Hines + */ + +#ifndef __ARCH_ARM_REGISTERS_HH__ +#define __ARCH_ARM_REGISTERS_HH__ + +#include "arch/arm/max_inst_regs.hh" +#include "arch/arm/miscregs.hh" + +namespace ArmISA { + +using ArmISAInst::MaxInstSrcRegs; +using ArmISAInst::MaxInstDestRegs; + +typedef uint8_t RegIndex; + +typedef uint64_t IntReg; + +// floating point register file entry type +typedef uint32_t FloatRegBits; +typedef float FloatReg; + +// cop-0/cop-1 system control register +typedef uint64_t MiscReg; + +// Constants Related to the number of registers +const int NumIntArchRegs = 16; +const int NumIntSpecialRegs = 19; +const int NumFloatArchRegs = 16; +const int NumFloatSpecialRegs = 5; +const int NumInternalProcRegs = 0; + +const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; +const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; + +const int NumMiscRegs = NUM_MISCREGS; + + +// semantically meaningful register indices +const int ReturnValueReg = 0; +const int ReturnValueReg1 = 1; +const int ReturnValueReg2 = 2; +const int ArgumentReg0 = 0; +const int ArgumentReg1 = 1; +const int ArgumentReg2 = 2; +const int ArgumentReg3 = 3; +const int FramePointerReg = 11; +const int StackPointerReg = 13; +const int ReturnAddressReg = 14; +const int PCReg = 15; + +const int ZeroReg = NumIntArchRegs; +const int AddrReg = ZeroReg + 1; // Used to generate address for uops + +const int SyscallNumReg = ReturnValueReg; +const int SyscallPseudoReturnReg = ReturnValueReg; +const int SyscallSuccessReg = ReturnValueReg; + +// These help enumerate all the registers for dependence tracking. +const int FP_Base_DepTag = NumIntRegs; +const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; + +typedef union { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; +} AnyReg; + +enum FPControlRegNums { + FIR = NumFloatArchRegs, + FCCR, + FEXR, + FENR, + FCSR +}; + +enum FCSRBits { + Inexact = 1, + Underflow, + Overflow, + DivideByZero, + Invalid, + Unimplemented +}; + +enum FCSRFields { + Flag_Field = 1, + Enable_Field = 6, + Cause_Field = 11 +}; + +enum MiscIntRegNums { + zero_reg = NumIntArchRegs, + addr_reg, + + rhi, + rlo, + + r8_fiq, /* FIQ mode register bank */ + r9_fiq, + r10_fiq, + r11_fiq, + r12_fiq, + + r13_fiq, /* FIQ mode SP and LR */ + r14_fiq, + + r13_irq, /* IRQ mode SP and LR */ + r14_irq, + + r13_svc, /* SVC mode SP and LR */ + r14_svc, + + r13_undef, /* UNDEF mode SP and LR */ + r14_undef, + + r13_abt, /* ABT mode SP and LR */ + r14_abt +}; + +} // namespace ArmISA + +#endif diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 3a0fdf2a5..2c4e1291c 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -113,29 +113,9 @@ namespace ArmISA ROR }; - typedef uint8_t RegIndex; - - typedef uint64_t IntReg; typedef uint64_t LargestRead; // Need to use 64 bits to make sure that read requests get handled properly - // floating point register file entry type - typedef uint32_t FloatReg32; - typedef uint64_t FloatReg64; - typedef uint64_t FloatRegBits; - - typedef double FloatRegVal; - typedef double FloatReg; - - // cop-0/cop-1 system control register - typedef uint64_t MiscReg; - - typedef union { - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - typedef int RegContextParam; typedef int RegContextVal; diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 93f207ec7..a2f0ef170 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -113,6 +113,18 @@ namespace ArmISA { { return NoFault; } + + static inline void + copyRegs(ThreadContext *src, ThreadContext *dest) + { + panic("Copy Regs Not Implemented Yet\n"); + } + + static inline void + copyMiscRegs(ThreadContext *src, ThreadContext *dest) + { + panic("Copy Misc. Regs Not Implemented Yet\n"); + } }; diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index fcb7ea7e4..6f002c05b 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -344,7 +344,7 @@ def p_def_operands(t): error(t.lexer.lineno, 'error: operand types must be defined before operands') try: - userDict = eval('{' + t[3] + '}') + userDict = eval('{' + t[3] + '}', exportContext) except Exception, exc: error(t.lexer.lineno, 'error: %s in def operands block "%s".' % (exc, t[3])) @@ -1173,6 +1173,39 @@ def buildOperandTypeMap(userDict, lineno): # (e.g., "32-bit integer register"). # class Operand(object): + def buildReadCode(self, func = None): + code = self.read_code % {"name": self.base_name, + "func": func, + "op_idx": self.src_reg_idx, + "reg_idx": self.reg_spec, + "size": self.size, + "ctype": self.ctype} + if self.size != self.dflt_size: + return '%s = bits(%s, %d, 0);\n' % \ + (self.base_name, code, self.size-1) + else: + return '%s = %s;\n' % \ + (self.base_name, code) + + def buildWriteCode(self, func = None): + if (self.size != self.dflt_size and self.is_signed): + final_val = 'sext<%d>(%s)' % (self.size, self.base_name) + else: + final_val = self.base_name + code = self.write_code % {"name": self.base_name, + "func": func, + "op_idx": self.dest_reg_idx, + "reg_idx": self.reg_spec, + "size": self.size, + "ctype": self.ctype, + "final_val": final_val} + return ''' + { + %s final_val = %s; + %s; + if (traceData) { traceData->setData(final_val); } + }''' % (self.dflt_ctype, final_val, code) + def __init__(self, full_name, ext, is_src, is_dest): self.full_name = full_name self.ext = ext @@ -1234,9 +1267,6 @@ class Operand(object): def isControlReg(self): return 0 - def isIControlReg(self): - return 0 - def getFlags(self): # note the empty slice '[:]' gives us a copy of self.flags[0] # instead of a reference to it @@ -1272,6 +1302,8 @@ class IntRegOperand(Operand): def makeRead(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read integer register as FP') + if self.read_code != None: + return self.buildReadCode('readIntRegOperand') if (self.size == self.dflt_size): return '%s = xc->readIntRegOperand(this, %d);\n' % \ (self.base_name, self.src_reg_idx) @@ -1288,6 +1320,8 @@ class IntRegOperand(Operand): def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to write integer register as FP') + if self.write_code != None: + return self.buildWriteCode('setIntRegOperand') if (self.size != self.dflt_size and self.is_signed): final_val = 'sext<%d>(%s)' % (self.size, self.base_name) else: @@ -1319,27 +1353,15 @@ class FloatRegOperand(Operand): def makeRead(self): bit_select = 0 - width = 0; - if (self.ctype == 'float'): - func = 'readFloatRegOperand' - width = 32; - elif (self.ctype == 'double'): + if (self.ctype == 'float' or self.ctype == 'double'): func = 'readFloatRegOperand' - width = 64; else: func = 'readFloatRegOperandBits' - if (self.ctype == 'uint32_t'): - width = 32; - elif (self.ctype == 'uint64_t'): - width = 64; if (self.size != self.dflt_size): bit_select = 1 - if width: - base = 'xc->%s(this, %d, %d)' % \ - (func, self.src_reg_idx, width) - else: - base = 'xc->%s(this, %d)' % \ - (func, self.src_reg_idx) + base = 'xc->%s(this, %d)' % (func, self.src_reg_idx) + if self.read_code != None: + return self.buildReadCode(func) if bit_select: return '%s = bits(%s, %d, 0);\n' % \ (self.base_name, base, self.size-1) @@ -1349,34 +1371,23 @@ class FloatRegOperand(Operand): def makeWrite(self): final_val = self.base_name final_ctype = self.ctype - widthSpecifier = '' - width = 0 - if (self.ctype == 'float'): - width = 32 - func = 'setFloatRegOperand' - elif (self.ctype == 'double'): - width = 64 + if (self.ctype == 'float' or self.ctype == 'double'): func = 'setFloatRegOperand' - elif (self.ctype == 'uint32_t'): - func = 'setFloatRegOperandBits' - width = 32 - elif (self.ctype == 'uint64_t'): + elif (self.ctype == 'uint32_t' or self.ctype == 'uint64_t'): func = 'setFloatRegOperandBits' - width = 64 else: func = 'setFloatRegOperandBits' final_ctype = 'uint%d_t' % self.dflt_size if (self.size != self.dflt_size and self.is_signed): final_val = 'sext<%d>(%s)' % (self.size, self.base_name) - if width: - widthSpecifier = ', %d' % width + if self.write_code != None: + return self.buildWriteCode(func) wb = ''' { %s final_val = %s; - xc->%s(this, %d, final_val%s);\n + xc->%s(this, %d, final_val);\n if (traceData) { traceData->setData(final_val); } - }''' % (final_ctype, final_val, func, self.dest_reg_idx, - widthSpecifier) + }''' % (final_ctype, final_val, func, self.dest_reg_idx) return wb class ControlRegOperand(Operand): @@ -1400,6 +1411,8 @@ class ControlRegOperand(Operand): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read control register as FP') + if self.read_code != None: + return self.buildReadCode('readMiscRegOperand') base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx if self.size == self.dflt_size: return '%s = %s;\n' % (self.base_name, base) @@ -1410,54 +1423,21 @@ class ControlRegOperand(Operand): def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to write control register as FP') + if self.write_code != None: + return self.buildWriteCode('setMiscRegOperand') wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ (self.dest_reg_idx, self.base_name) wb += 'if (traceData) { traceData->setData(%s); }' % \ self.base_name return wb -class IControlRegOperand(Operand): - def isReg(self): - return 1 - - def isIControlReg(self): - return 1 - - def makeConstructor(self): - c = '' - if self.is_src: - c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \ - (self.src_reg_idx, self.reg_spec) - if self.is_dest: - c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \ - (self.dest_reg_idx, self.reg_spec) - return c - - def makeRead(self): - bit_select = 0 - if (self.ctype == 'float' or self.ctype == 'double'): - error(0, 'Attempt to read control register as FP') - base = 'xc->readMiscReg(%s)' % self.reg_spec - if self.size == self.dflt_size: - return '%s = %s;\n' % (self.base_name, base) - else: - return '%s = bits(%s, %d, 0);\n' % \ - (self.base_name, base, self.size-1) - - def makeWrite(self): - if (self.ctype == 'float' or self.ctype == 'double'): - error(0, 'Attempt to write control register as FP') - wb = 'xc->setMiscReg(%s, %s);\n' % \ - (self.reg_spec, self.base_name) - wb += 'if (traceData) { traceData->setData(%s); }' % \ - self.base_name - return wb - class ControlBitfieldOperand(ControlRegOperand): def makeRead(self): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read control register as FP') + if self.read_code != None: + return self.buildReadCode('readMiscReg') base = 'xc->readMiscReg(%s)' % self.reg_spec name = self.base_name return '%s = bits(%s, %s_HI, %s_LO);' % \ @@ -1466,6 +1446,8 @@ class ControlBitfieldOperand(ControlRegOperand): def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to write control register as FP') + if self.write_code != None: + return self.buildWriteCode('setMiscReg') base = 'xc->readMiscReg(%s)' % self.reg_spec name = self.base_name wb_val = 'insertBits(%s, %s_HI, %s_LO, %s)' % \ @@ -1493,9 +1475,13 @@ class MemOperand(Operand): return c def makeRead(self): + if self.read_code != None: + return self.buildReadCode() return '' def makeWrite(self): + if self.write_code != None: + return self.buildWriteCode() return '' # Return the memory access size *in bits*, suitable for @@ -1508,9 +1494,13 @@ class UPCOperand(Operand): return '' def makeRead(self): + if self.read_code != None: + return self.buildReadCode('readMicroPC') return '%s = xc->readMicroPC();\n' % self.base_name def makeWrite(self): + if self.write_code != None: + return self.buildWriteCode('setMicroPC') return 'xc->setMicroPC(%s);\n' % self.base_name class NUPCOperand(Operand): @@ -1518,9 +1508,13 @@ class NUPCOperand(Operand): return '' def makeRead(self): + if self.read_code != None: + return self.buildReadCode('readNextMicroPC') return '%s = xc->readNextMicroPC();\n' % self.base_name def makeWrite(self): + if self.write_code != None: + return self.buildWriteCode('setNextMicroPC') return 'xc->setNextMicroPC(%s);\n' % self.base_name class NPCOperand(Operand): @@ -1528,9 +1522,13 @@ class NPCOperand(Operand): return '' def makeRead(self): + if self.read_code != None: + return self.buildReadCode('readNextPC') return '%s = xc->readNextPC();\n' % self.base_name def makeWrite(self): + if self.write_code != None: + return self.buildWriteCode('setNextPC') return 'xc->setNextPC(%s);\n' % self.base_name class NNPCOperand(Operand): @@ -1538,16 +1536,33 @@ class NNPCOperand(Operand): return '' def makeRead(self): + if self.read_code != None: + return self.buildReadCode('readNextNPC') return '%s = xc->readNextNPC();\n' % self.base_name def makeWrite(self): + if self.write_code != None: + return self.buildWriteCode('setNextNPC') return 'xc->setNextNPC(%s);\n' % self.base_name def buildOperandNameMap(userDict, lineno): global operandNameMap operandNameMap = {} for (op_name, val) in userDict.iteritems(): - (base_cls_name, dflt_ext, reg_spec, flags, sort_pri) = val + (base_cls_name, dflt_ext, reg_spec, flags, sort_pri) = val[:5] + if len(val) > 5: + read_code = val[5] + else: + read_code = None + if len(val) > 6: + write_code = val[6] + else: + write_code = None + if len(val) > 7: + error(lineno, + 'error: too many attributes for operand "%s"' % + base_cls_name) + (dflt_size, dflt_ctype, dflt_is_signed) = operandTypeMap[dflt_ext] # Canonical flag structure is a triple of lists, where each list # indicates the set of flags implied by this operand always, when @@ -1572,7 +1587,8 @@ def buildOperandNameMap(userDict, lineno): # Accumulate attributes of new operand class in tmp_dict tmp_dict = {} for attr in ('dflt_ext', 'reg_spec', 'flags', 'sort_pri', - 'dflt_size', 'dflt_ctype', 'dflt_is_signed'): + 'dflt_size', 'dflt_ctype', 'dflt_is_signed', + 'read_code', 'write_code'): tmp_dict[attr] = eval(attr) tmp_dict['base_name'] = op_name # New class name will be e.g. "IntReg_Ra" diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 0b470def6..ffc1f18eb 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -34,10 +34,7 @@ Import('*') if env['TARGET_ISA'] == 'mips': Source('faults.cc') - Source('regfile/int_regfile.cc') - Source('regfile/float_regfile.cc') - Source('regfile/misc_regfile.cc') - Source('regfile/regfile.cc') + Source('isa.cc') Source('tlb.cc') Source('pagetable.cc') Source('utility.cc') diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 63884e837..347d041a3 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -435,7 +435,6 @@ void InterruptFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(MipsPRA,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; @@ -471,7 +470,6 @@ void ReservedInstructionFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(MipsPRA,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/isa.cc index aee4fab4d..f03a72e98 100644 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/isa.cc @@ -1,6 +1,5 @@ /* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,26 +25,22 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Korey Sewell - * Jaidev Patwardhan + * Authors: Gabe Black */ -#include "base/bitfield.hh" - -#include "arch/mips/regfile/misc_regfile.hh" +#include "arch/mips/isa.hh" #include "arch/mips/mt_constants.hh" +#include "arch/mips/mt.hh" #include "arch/mips/pra_constants.hh" - -#include "cpu/thread_context.hh" +#include "base/bitfield.hh" #include "cpu/base.hh" -#include "cpu/exetrace.hh" - -//#include "params/DerivO3CPU.hh" +#include "cpu/thread_context.hh" -using namespace std; -using namespace MipsISA; +namespace MipsISA +{ -std::string MiscRegFile::miscRegNames[NumMiscRegs] = +std::string +ISA::miscRegNames[NumMiscRegs] = { "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "", "Random", "VPEControl", "VPEConf0", "VPEConf1", @@ -91,19 +86,19 @@ std::string MiscRegFile::miscRegNames[NumMiscRegs] = "LLFlag" }; -MiscRegFile::MiscRegFile() +ISA::ISA() { init(); } -MiscRegFile::MiscRegFile(BaseCPU *_cpu) +ISA::ISA(BaseCPU *_cpu) { cpu = _cpu; init(); } void -MiscRegFile::init() +ISA::init() { miscRegFile.resize(NumMiscRegs); bankType.resize(NumMiscRegs); @@ -122,7 +117,7 @@ MiscRegFile::init() } void -MiscRegFile::clear(unsigned tid_or_vpn) +ISA::clear(unsigned tid_or_vpn) { for(int i = 0; i < NumMiscRegs; i++) { miscRegFile[i][tid_or_vpn] = 0; @@ -131,7 +126,7 @@ MiscRegFile::clear(unsigned tid_or_vpn) } void -MiscRegFile::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) +ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) { // Initialize all Per-VPE regs uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask, @@ -167,20 +162,10 @@ MiscRegFile::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) } } -int MiscRegFile::getInstAsid() -{ - MiscReg Entry_Hi = readRegNoEffect(EntryHi); - return bits(Entry_Hi,EntryHi_ASID_HI,EntryHi_ASID_LO); -} -int MiscRegFile:: getDataAsid() -{ - MiscReg EHi = readRegNoEffect(EntryHi); - return bits(EHi,EntryHi_ASID_HI,EntryHi_ASID_LO); -} //@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H) void -MiscRegFile::reset(std::string core_name, ThreadID num_threads, +ISA::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes, BaseCPU *_cpu) { DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n", @@ -196,33 +181,33 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, // =================================================== DPRINTF(MipsPRA, "Initializing CP0 State.... "); - MiscReg ProcID = readRegNoEffect(PRId); + MiscReg ProcID = readMiscRegNoEffect(PRId); replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,cp.CP0_PRId_CompanyOptions); replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,cp.CP0_PRId_CompanyID); replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,cp.CP0_PRId_ProcessorID); replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,cp.CP0_PRId_Revision); - setRegNoEffect(PRId,ProcID); + setMiscRegNoEffect(PRId,ProcID); // Now, create Write Mask for ProcID register MiscReg ProcID_Mask = 0; // Read-Only register replaceBits(ProcID_Mask,0,32,0); setRegMask(PRId,ProcID_Mask); // Config - MiscReg cfg = readRegNoEffect(Config); + MiscReg cfg = readMiscRegNoEffect(Config); replaceBits(cfg, Config_BE_HI, Config_BE_LO, cp.CP0_Config_BE); replaceBits(cfg, Config_AT_HI, Config_AT_LO, cp.CP0_Config_AT); replaceBits(cfg, Config_AR_HI, Config_AR_LO, cp.CP0_Config_AR); replaceBits(cfg, Config_MT_HI, Config_MT_LO, cp.CP0_Config_MT); replaceBits(cfg, Config_VI_HI, Config_VI_LO, cp.CP0_Config_VI); replaceBits(cfg, Config_M, 1); - setRegNoEffect(Config, cfg); + setMiscRegNoEffect(Config, cfg); // Now, create Write Mask for Config register MiscReg cfg_Mask = 0x7FFF0007; replaceBits(cfg_Mask,0,32,0); setRegMask(Config,cfg_Mask); // Config1 - MiscReg cfg1 = readRegNoEffect(Config1); + MiscReg cfg1 = readMiscRegNoEffect(Config1); replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, cp.CP0_Config1_MMU); replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS); @@ -238,14 +223,14 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, cp.CP0_Config1_C2); replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, cp.CP0_Config1_PC); replaceBits(cfg1, Config1_M, cp.CP0_Config1_M); - setRegNoEffect(Config1, cfg1); + setMiscRegNoEffect(Config1, cfg1); // Now, create Write Mask for Config register MiscReg cfg1_Mask = 0; // Read Only Register replaceBits(cfg1_Mask,0,32,0); setRegMask(Config1,cfg1_Mask); // Config2 - MiscReg cfg2 = readRegNoEffect(Config2); + MiscReg cfg2 = readMiscRegNoEffect(Config2); replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, cp.CP0_Config2_TU); replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, cp.CP0_Config2_TS); replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, cp.CP0_Config2_TL); @@ -255,14 +240,14 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, cp.CP0_Config2_SL); replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, cp.CP0_Config2_SA); replaceBits(cfg2, Config2_M, cp.CP0_Config2_M); - setRegNoEffect(Config2, cfg2); + setMiscRegNoEffect(Config2, cfg2); // Now, create Write Mask for Config register MiscReg cfg2_Mask = 0x7000F000; // Read Only Register replaceBits(cfg2_Mask,0,32,0); setRegMask(Config2,cfg2_Mask); // Config3 - MiscReg cfg3 = readRegNoEffect(Config3); + MiscReg cfg3 = readMiscRegNoEffect(Config3); replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, cp.CP0_Config3_DSPP); replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, cp.CP0_Config3_LPA); replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, cp.CP0_Config3_VEIC); @@ -271,17 +256,17 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, cp.CP0_Config3_MT); replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, cp.CP0_Config3_SM); replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, cp.CP0_Config3_TL); - setRegNoEffect(Config3, cfg3); + setMiscRegNoEffect(Config3, cfg3); // Now, create Write Mask for Config register MiscReg cfg3_Mask = 0; // Read Only Register replaceBits(cfg3_Mask,0,32,0); setRegMask(Config3,cfg3_Mask); // EBase - CPUNum - MiscReg EB = readRegNoEffect(EBase); + MiscReg EB = readMiscRegNoEffect(EBase); replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, cp.CP0_EBase_CPUNum); replaceBits(EB, 31, 31, 1); - setRegNoEffect(EBase, EB); + setMiscRegNoEffect(EBase, EB); // Now, create Write Mask for Config register MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the // entire register is read only @@ -289,63 +274,63 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, setRegMask(EBase,EB_Mask); // SRS Control - HSS (Highest Shadow Set) - MiscReg SC = readRegNoEffect(SRSCtl); + MiscReg SC = readMiscRegNoEffect(SRSCtl); replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,cp.CP0_SrsCtl_HSS); - setRegNoEffect(SRSCtl, SC); + setMiscRegNoEffect(SRSCtl, SC); // Now, create Write Mask for the SRS Ctl register MiscReg SC_Mask = 0x0000F3C0; replaceBits(SC_Mask,0,32,0); setRegMask(SRSCtl,SC_Mask); // IntCtl - IPTI, IPPCI - MiscReg IC = readRegNoEffect(IntCtl); + MiscReg IC = readMiscRegNoEffect(IntCtl); replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,cp.CP0_IntCtl_IPTI); replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,cp.CP0_IntCtl_IPPCI); - setRegNoEffect(IntCtl, IC); + setMiscRegNoEffect(IntCtl, IC); // Now, create Write Mask for the IntCtl register MiscReg IC_Mask = 0x000003E0; replaceBits(IC_Mask,0,32,0); setRegMask(IntCtl,IC_Mask); // Watch Hi - M - FIXME (More than 1 Watch register) - MiscReg WHi = readRegNoEffect(WatchHi0); + MiscReg WHi = readMiscRegNoEffect(WatchHi0); replaceBits(WHi, WatchHi_M, cp.CP0_WatchHi_M); - setRegNoEffect(WatchHi0, WHi); + setMiscRegNoEffect(WatchHi0, WHi); // Now, create Write Mask for the IntCtl register MiscReg wh_Mask = 0x7FFF0FFF; replaceBits(wh_Mask,0,32,0); setRegMask(WatchHi0,wh_Mask); // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair) - MiscReg PCtr = readRegNoEffect(PerfCnt0); + MiscReg PCtr = readMiscRegNoEffect(PerfCnt0); replaceBits(PCtr, PerfCntCtl_M, cp.CP0_PerfCtr_M); replaceBits(PCtr, PerfCntCtl_W, cp.CP0_PerfCtr_W); - setRegNoEffect(PerfCnt0, PCtr); + setMiscRegNoEffect(PerfCnt0, PCtr); // Now, create Write Mask for the IntCtl register MiscReg pc_Mask = 0x00007FF; replaceBits(pc_Mask,0,32,0); setRegMask(PerfCnt0,pc_Mask); // Random - MiscReg random = readRegNoEffect(CP0_Random); + MiscReg random = readMiscRegNoEffect(CP0_Random); random = 63; - setRegNoEffect(CP0_Random, random); + setMiscRegNoEffect(CP0_Random, random); // Now, create Write Mask for the IntCtl register MiscReg random_Mask = 0; replaceBits(random_Mask,0,32,0); setRegMask(CP0_Random,random_Mask); // PageGrain - MiscReg pagegrain = readRegNoEffect(PageGrain); + MiscReg pagegrain = readMiscRegNoEffect(PageGrain); replaceBits(pagegrain,PageGrain_ESP,cp.CP0_Config3_SP); - setRegNoEffect(PageGrain, pagegrain); + setMiscRegNoEffect(PageGrain, pagegrain); // Now, create Write Mask for the IntCtl register MiscReg pg_Mask = 0x10000000; replaceBits(pg_Mask,0,32,0); setRegMask(PageGrain,pg_Mask); // Status - MiscReg stat = readRegNoEffect(Status); + MiscReg stat = readMiscRegNoEffect(Status); // Only CU0 and IE are modified on a reset - everything else needs // to be controlled on a per CPU model basis @@ -358,7 +343,7 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, // Enable BEV bit on a reset replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1); - setRegNoEffect(Status, stat); + setMiscRegNoEffect(Status, stat); // Now, create Write Mask for the Status register MiscReg stat_Mask = 0xFF78FF17; replaceBits(stat_Mask,0,32,0); @@ -366,45 +351,45 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, // MVPConf0 - MiscReg mvp_conf0 = readRegNoEffect(MVPConf0); + MiscReg mvp_conf0 = readMiscRegNoEffect(MVPConf0); replaceBits(mvp_conf0, MVPC0_TCA, 1); replaceBits(mvp_conf0, MVPC0_PVPE_HI, MVPC0_PVPE_LO, num_vpes - 1); replaceBits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO, num_threads - 1); - setRegNoEffect(MVPConf0, mvp_conf0); + setMiscRegNoEffect(MVPConf0, mvp_conf0); // VPEConf0 - MiscReg vpe_conf0 = readRegNoEffect(VPEConf0); + MiscReg vpe_conf0 = readMiscRegNoEffect(VPEConf0); replaceBits(vpe_conf0, VPEC0_MVP, 1); - setRegNoEffect(VPEConf0, vpe_conf0); + setMiscRegNoEffect(VPEConf0, vpe_conf0); // TCBind for (ThreadID tid = 0; tid < num_threads; tid++) { - MiscReg tc_bind = readRegNoEffect(TCBind, tid); + MiscReg tc_bind = readMiscRegNoEffect(TCBind, tid); replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid); - setRegNoEffect(TCBind, tc_bind, tid); + setMiscRegNoEffect(TCBind, tc_bind, tid); } // TCHalt - MiscReg tc_halt = readRegNoEffect(TCHalt); + MiscReg tc_halt = readMiscRegNoEffect(TCHalt); replaceBits(tc_halt, TCH_H, 0); - setRegNoEffect(TCHalt, tc_halt); + setMiscRegNoEffect(TCHalt, tc_halt); /*for (ThreadID tid = 1; tid < num_threads; tid++) { // Set TCHalt Halt bit to 1 for all other threads - tc_halt = readRegNoEffect(TCHalt, tid); + tc_halt = readMiscRegNoEffect(TCHalt, tid); replaceBits(tc_halt, TCH_H, 1); setReg(TCHalt, tc_halt, tid); }*/ // TCStatus // Set TCStatus Activated to 1 for the initial thread that is running - MiscReg tc_status = readRegNoEffect(TCStatus); + MiscReg tc_status = readMiscRegNoEffect(TCStatus); replaceBits(tc_status, TCS_A, 1); - setRegNoEffect(TCStatus, tc_status); + setMiscRegNoEffect(TCStatus, tc_status); // Set Dynamically Allocatable bit to 1 for all other threads for (ThreadID tid = 1; tid < num_threads; tid++) { - tc_status = readRegNoEffect(TCStatus, tid); + tc_status = readMiscRegNoEffect(TCStatus, tid); replaceBits(tc_status, TCSTATUS_DA, 1); - setRegNoEffect(TCStatus, tc_status, tid); + setMiscRegNoEffect(TCStatus, tc_status, tid); } @@ -439,14 +424,14 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, } inline unsigned -MiscRegFile::getVPENum(ThreadID tid) +ISA::getVPENum(ThreadID tid) { unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid]; return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO); } MiscReg -MiscRegFile::readRegNoEffect(int reg_idx, ThreadID tid) +ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid) { int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) @@ -461,7 +446,7 @@ MiscRegFile::readRegNoEffect(int reg_idx, ThreadID tid) // Status to TCStatus depending on current thread //template <class TC> MiscReg -MiscRegFile::readReg(int reg_idx, ThreadContext *tc, ThreadID tid) +ISA::readMiscReg(int reg_idx, ThreadContext *tc, ThreadID tid) { int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) @@ -480,7 +465,7 @@ MiscRegFile::readReg(int reg_idx, ThreadContext *tc, ThreadID tid) } void -MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid) +ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid) { int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) @@ -492,8 +477,9 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid) miscRegFile[misc_reg][reg_sel] = val; } + void -MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid) +ISA::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid) { // return; int misc_reg = reg_idx - Ctrl_Base_DepTag; @@ -511,7 +497,7 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid) // with care! //template <class TC> void -MiscRegFile::setReg(int reg_idx, const MiscReg &val, +ISA::setMiscReg(int reg_idx, const MiscReg &val, ThreadContext *tc, ThreadID tid) { int misc_reg = reg_idx - Ctrl_Base_DepTag; @@ -529,13 +515,14 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val, scheduleCP0Update(1); } + /** * This method doesn't need to adjust the Control Register Offset * since it has already been done in the calling method * (setRegWithEffect) */ MiscReg -MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) +ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) { MiscReg retVal = val; @@ -553,8 +540,9 @@ MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) val, miscRegFile[misc_reg][reg_sel], retVal); return retVal; } + void -MiscRegFile::scheduleCP0Update(int delay) +ISA::scheduleCP0Update(int delay) { if (!cp0Updated) { cp0Updated = true; @@ -566,19 +554,19 @@ MiscRegFile::scheduleCP0Update(int delay) } void -MiscRegFile::updateCPU() +ISA::updateCPU() { /////////////////////////////////////////////////////////////////// // // EVALUATE CP0 STATE FOR MIPS MT // /////////////////////////////////////////////////////////////////// - unsigned mvp_conf0 = readRegNoEffect(MVPConf0); + unsigned mvp_conf0 = readMiscRegNoEffect(MVPConf0); ThreadID num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1; for (ThreadID tid = 0; tid < num_threads; tid++) { - MiscReg tc_status = readRegNoEffect(TCStatus, tid); - MiscReg tc_halt = readRegNoEffect(TCHalt, tid); + MiscReg tc_status = readMiscRegNoEffect(TCStatus, tid); + MiscReg tc_halt = readMiscRegNoEffect(TCHalt, tid); //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) { @@ -594,12 +582,12 @@ MiscRegFile::updateCPU() cp0Updated = false; } -MiscRegFile::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) +ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) { } void -MiscRegFile::CP0Event::process() +ISA::CP0Event::process() { switch (cp0EventType) { @@ -612,20 +600,22 @@ MiscRegFile::CP0Event::process() } const char * -MiscRegFile::CP0Event::description() const +ISA::CP0Event::description() const { return "Coprocessor-0 event"; } void -MiscRegFile::CP0Event::scheduleEvent(int delay) +ISA::CP0Event::scheduleEvent(int delay) { cpu->reschedule(this, curTick + cpu->ticks(delay), true); } void -MiscRegFile::CP0Event::unscheduleEvent() +ISA::CP0Event::unscheduleEvent() { if (scheduled()) squash(); } + +} diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/isa.hh index 633ea7efb..15c043dc0 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/isa.hh @@ -1,6 +1,5 @@ /* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,33 +25,33 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Korey Sewell - * Jaidev Patwardhan + * Authors: Gabe Black */ -#ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ +#ifndef __ARCH_MIPS_ISA_HH__ +#define __ARCH_MIPS_ISA_HH__ -#include "arch/mips/isa_traits.hh" +#include <string> +#include <queue> +#include <vector> + +#include "arch/mips/registers.hh" #include "arch/mips/types.hh" -#include "arch/mips/mt.hh" -#include "arch/mips/mt_constants.hh" -#include "base/bitfield.hh" #include "sim/eventq.hh" -#include <queue> +#include "sim/faults.hh" -class Params; class BaseCPU; +class Checkpoint; +class EventManager; +class ThreadContext; namespace MipsISA { - class MiscRegFile { + class ISA + { public: - // Give RegFile object, private access - friend class RegFile; - // The MIPS name for this file is CP0 or Coprocessor 0 - typedef MiscRegFile CP0; + typedef ISA CP0; protected: enum BankType { @@ -68,8 +67,8 @@ namespace MipsISA BaseCPU *cpu; public: - MiscRegFile(); - MiscRegFile(BaseCPU *_cpu); + ISA(); + ISA(BaseCPU *_cpu); void init(); @@ -91,23 +90,20 @@ namespace MipsISA //@TODO: MIPS MT's register view automatically connects // Status to TCStatus depending on current thread void updateCP0ReadView(int misc_reg, ThreadID tid) { } - MiscReg readRegNoEffect(int misc_reg, ThreadID tid = 0); + MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); //template <class TC> - MiscReg readReg(int misc_reg, - ThreadContext *tc, ThreadID tid = 0); + MiscReg readMiscReg(int misc_reg, + ThreadContext *tc, ThreadID tid = 0); MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val); void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0); - void setRegNoEffect(int misc_reg, const MiscReg &val, - ThreadID tid = 0); + void setMiscRegNoEffect(int misc_reg, const MiscReg &val, + ThreadID tid = 0); //template <class TC> - void setReg(int misc_reg, const MiscReg &val, - ThreadContext *tc, ThreadID tid = 0); - - int getInstAsid(); - int getDataAsid(); + void setMiscReg(int misc_reg, const MiscReg &val, + ThreadContext *tc, ThreadID tid = 0); ////////////////////////////////////////////////////////// // @@ -128,7 +124,7 @@ namespace MipsISA class CP0Event : public Event { protected: - MiscRegFile::CP0 *cp0; + ISA::CP0 *cp0; BaseCPU *cpu; CP0EventType cp0EventType; Fault fault; @@ -161,7 +157,24 @@ namespace MipsISA std::queue<CP0Event*> cp0EventRemoveList; static std::string miscRegNames[NumMiscRegs]; + + public: + + int + flattenIntIndex(int reg) + { + return reg; + } + + int + flattenFloatIndex(int reg) + { + return reg; + } + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); }; -} // namespace MipsISA +} #endif diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index 74200a74a..52fcd0724 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -104,25 +104,14 @@ output exec {{ Trace::InstRecord *traceData) { uint64_t mips_nan = 0; - T src_op = 0; - int size = sizeof(src_op) * 8; + assert(sizeof(T) == 4); for (int i = 0; i < inst->numSrcRegs(); i++) { - uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size); - - if (isNan(&src_bits, size) ) { - if (isSnan(&src_bits, size)) { - switch (size) - { - case 32: mips_nan = MIPS32_QNAN; break; - case 64: mips_nan = MIPS64_QNAN; break; - default: panic("Unsupported Floating Point Size (%d)", size); - } - } else { - mips_nan = src_bits; - } + uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0); - xc->setFloatRegOperandBits(inst, 0, mips_nan, size); + if (isNan(&src_bits, 32) ) { + mips_nan = MIPS32_QNAN; + xc->setFloatRegOperandBits(inst, 0, mips_nan); if (traceData) { traceData->setData(mips_nan); } return true; } @@ -137,18 +126,13 @@ output exec {{ { uint64_t mips_nan = 0; T src_op = dest_val; - int size = sizeof(src_op) * 8; + assert(sizeof(T) == 4); - if (isNan(&src_op, size)) { - switch (size) - { - case 32: mips_nan = MIPS32_QNAN; break; - case 64: mips_nan = MIPS64_QNAN; break; - default: panic("Unsupported Floating Point Size (%d)", size); - } + if (isNan(&src_op, 32)) { + mips_nan = MIPS32_QNAN; //Set value to QNAN - cpu->setFloatRegOperandBits(inst, 0, mips_nan, size); + cpu->setFloatRegOperandBits(inst, 0, mips_nan); //Read FCSR from FloatRegFile uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index aa1c8d8af..22eb3bf13 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -70,6 +70,7 @@ output exec {{ #include "arch/mips/isa_traits.hh" #include "arch/mips/utility.hh" #include "arch/mips/dsp.hh" +#include "arch/mips/mt.hh" #include "arch/mips/pra_constants.hh" #include "arch/mips/dt_constants.hh" #include "arch/mips/mt_constants.hh" diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 609708a13..c2733be9d 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -113,10 +113,7 @@ def operands {{ 'Index':('ControlReg','uw','MipsISA::Index',None,1), - #Special cases for when a Control Register Access is dependent on - #a combination of bitfield indices (handles MTCO & MFCO) - # Fixed to allow CP0 Register Offset - 'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1), + 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1), #MT Control Regs 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index 7522dcf0f..a8d5b07b6 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -143,7 +143,6 @@ namespace MipsISA NumInterruptLevels = INTLEVEL_EXTERNAL_MAX }; - // MIPS modes enum mode_type { @@ -154,53 +153,9 @@ namespace MipsISA mode_number // number of modes }; - inline mode_type getOperatingMode(MiscReg Stat) - { - if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) - return mode_kernel; - else{ - if((Stat & 0x18) == 0x8) - return mode_supervisor; - else if((Stat & 0x18) == 0x10) - return mode_user; - else return mode_number; - } - } - - // return a no-op instruction... used for instruction fetch faults const ExtMachInst NoopMachInst = 0x00000000; - // Constants Related to the number of registers - const int NumIntArchRegs = 32; - const int NumIntSpecialRegs = 9; - const int NumFloatArchRegs = 32; - const int NumFloatSpecialRegs = 5; - - const int MaxShadowRegSets = 16; // Maximum number of shadow register sets - const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs - const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// - - // Static instruction parameters - const int MaxInstSrcRegs = 10; - const int MaxInstDestRegs = 8; - - // semantically meaningful register indices - const int ZeroReg = 0; - const int AssemblerReg = 1; - const int SyscallSuccessReg = 7; - const int FirstArgumentReg = 4; - const int ReturnValueReg = 2; - - const int KernelReg0 = 26; - const int KernelReg1 = 27; - const int GlobalPointerReg = 28; - const int StackPointerReg = 29; - const int FramePointerReg = 30; - const int ReturnAddressReg = 31; - - const int SyscallPseudoReturnReg = 3; - const int LogVMPageSize = 13; // 8K bytes const int VMPageSize = (1 << LogVMPageSize); @@ -213,174 +168,6 @@ namespace MipsISA const int ANNOTE_NONE = 0; const uint32_t ITOUCH_ANNOTE = 0xffffffff; - - // These help enumerate all the registers for dependence tracking. - const int FP_Base_DepTag = NumIntRegs; - const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; - - // Enumerate names for 'Control' Registers in the CPU - // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 - // (Register Number-Register Select) Summary of Register - //------------------------------------------------------ - // The first set of names classify the CP0 names as Register Banks - // for easy indexing when using the 'RD + SEL' index combination - // in CP0 instructions. - enum MiscRegTags { - Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3 - MVPControl, - MVPConf0, - MVPConf1, - - CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15 - VPEControl, - VPEConf0, - VPEConf1, - YQMask, - VPESchedule, - VPEScheFBack, - VPEOpt, - - EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23 - TCStatus, - TCBind, - TCRestart, - TCHalt, - TCContext, - TCSchedule, - TCScheFBack, - - EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24 - - Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33 - ContextConfig, - - PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41 - PageGrain = Ctrl_Base_DepTag + 41, - - Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55 - SRSConf0, - SRSConf1, - SRSConf2, - SRSConf3, - SRSConf4, - - HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63 - - BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71 - - Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79 - - EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87 - - Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95 - - Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103 - IntCtl, - SRSCtl, - SRSMap, - - Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111 - - EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119 - - PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127, - EBase, - - Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135 - Config1, - Config2, - Config3, - Config4, - Config5, - Config6, - Config7, - - - LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143 - - WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151 - WatchLo1, - WatchLo2, - WatchLo3, - WatchLo4, - WatchLo5, - WatchLo6, - WatchLo7, - - WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159 - WatchHi1, - WatchHi2, - WatchHi3, - WatchHi4, - WatchHi5, - WatchHi6, - WatchHi7, - - XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167 - - //Bank 21: 168-175 - - //Bank 22: 176-183 - - Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191 - TraceControl1, - TraceControl2, - UserTraceData, - TraceBPC, - - DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199 - - PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207 - PerfCnt1, - PerfCnt2, - PerfCnt3, - PerfCnt4, - PerfCnt5, - PerfCnt6, - PerfCnt7, - - ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215 - - CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223 - CacheErr1, - CacheErr2, - CacheErr3, - - TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231 - DataLo1, - TagLo2, - DataLo3, - TagLo4, - DataLo5, - TagLo6, - DataLo7, - - TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239 - DataHi1, - TagHi2, - DataHi3, - TagHi4, - DataHi5, - TagHi6, - DataHi7, - - - ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247 - - DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256 - - LLFlag = Ctrl_Base_DepTag + 257, - - NumControlRegs - }; - - const int TotalDataRegs = NumIntRegs + NumFloatRegs; - - const int NumMiscRegs = NumControlRegs; - - const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; - - }; #endif // __ARCH_MIPS_ISA_TRAITS_HH__ diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index 021b8cf73..e202a11aa 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -37,7 +37,7 @@ * ISA-specific helper functions for locked memory accesses. */ -#include "arch/isa_traits.hh" +#include "arch/registers.hh" #include "base/misc.hh" #include "base/trace.hh" #include "mem/request.hh" diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc index 80d856b0c..21847378f 100755 --- a/src/arch/mips/mips_core_specific.cc +++ b/src/arch/mips/mips_core_specific.cc @@ -109,19 +109,4 @@ MipsISA::processInterrupts(CPU *cpu) */ } - -/*int -MipsISA::MiscRegFile::getInstAsid() -{ - return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); -} - -int -MipsISA::MiscRegFile::getDataAsid() -{ - return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); - }*/ - - - #endif // FULL_SYSTEM || BARE_IRON diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh index 8b4c9f908..b581d5cf0 100755 --- a/src/arch/mips/mt.hh +++ b/src/arch/mips/mt.hh @@ -37,9 +37,10 @@ * ISA-specific helper functions for multithreaded execution. */ -#include "arch/isa_traits.hh" #include "arch/mips/faults.hh" +#include "arch/mips/isa_traits.hh" #include "arch/mips/mt_constants.hh" +#include "arch/mips/registers.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "base/misc.hh" diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc deleted file mode 100644 index 908302866..000000000 --- a/src/arch/mips/regfile.cc +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - * Korey Sewell - */ - -#ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_REGFILE_HH__ - -#include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -#include "arch/mips/mt.hh" -#include "arch/mips/regfile/int_regfile.hh" -#include "arch/mips/regfile/float_regfile.hh" -#include "arch/mips/regfile/misc_regfile.hh" -#include "sim/faults.hh" - -class Checkpoint; -class ThreadContext; - -using namespace MipsISA; - -void RegFile::clear() -{ - intRegFile.clear(); - floatRegFile.clear(); - miscRegFile.clear(); -} - -void -RegFile::reset(std::string core_name, ThreadID num_threads, - unsigned num_vpes) -{ - bzero(&intRegFile, sizeof(intRegFile)); - bzero(&floatRegFile, sizeof(floatRegFile)); - miscRegFile.reset(core_name, num_threads, num_vpes); -} - -IntReg RegFile::readIntReg(int intReg) -{ - return intRegFile.readReg(intReg); -} - -Fault RegFile::setIntReg(int intReg, const IntReg &val) -{ - return intRegFile.setReg(intReg, val); -} - -MiscReg -RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid = 0) -{ - return miscRegFile.readRegNoEffect(miscReg, tid); -} - -MiscReg -RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid = 0) -{ - return miscRegFile.readReg(miscReg, tc, tid); -} - -void -RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid = 0) -{ - miscRegFile.setRegNoEffect(miscReg, val, tid); -} - -void -RegFile::setMiscReg(int miscReg, const MiscReg &val, - ThreadContext *tc, ThreadID tid = 0) -{ - miscRegFile.setReg(miscReg, val, tc, tid); -} - -FloatRegVal RegFile::readFloatReg(int floatReg) -{ - return floatRegFile.readReg(floatReg,SingleWidth); -} - -FloatRegVal RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg,width); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg) -{ - return floatRegFile.readRegBits(floatReg,SingleWidth); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg,width); -} - -Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val) -{ - return floatRegFile.setReg(floatReg, val, SingleWidth); -} - -Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width) -{ - return floatRegFile.setReg(floatReg, val, width); -} - -Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) -{ - return floatRegFile.setRegBits(floatReg, val, SingleWidth); -} - -Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - return floatRegFile.setRegBits(floatReg, val, width); -} - -Addr RegFile::readPC() -{ - return pc; -} - -void RegFile::setPC(Addr val) -{ - pc = val; -} - -Addr RegFile::readNextPC() -{ - return npc; -} - -void RegFile::setNextPC(Addr val) -{ - npc = val; -} - -Addr RegFile::readNextNPC() -{ - return nnpc; -} - -void RegFile::setNextNPC(Addr val) -{ - nnpc = val; -} - -void -RegFile::serialize(std::ostream &os) -{ - intRegFile.serialize(os); - floatRegFile.serialize(os); - miscRegFile.serialize(os); - - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - - -void -RegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); - miscRegFile.unserialize(cp, section); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); - -} - -static inline int flattenIntIndex(ThreadContext * tc, int reg) -{ - return reg; -} - -void -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Regs Not Implemented Yet\n"); -} - -void -MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} diff --git a/src/arch/mips/regfile/float_regfile.cc b/src/arch/mips/regfile/float_regfile.cc deleted file mode 100644 index 2b32bd3af..000000000 --- a/src/arch/mips/regfile/float_regfile.cc +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Korey Sewell - */ - -#include "arch/mips/regfile/float_regfile.hh" -#include "sim/serialize.hh" - -using namespace MipsISA; -using namespace std; - -void -FloatRegFile::clear() -{ - bzero(®s, sizeof(regs)); -} - -double -FloatRegFile::readReg(int floatReg, int width, ThreadID tid) -{ - switch(width) - { - case SingleWidth: - { - void *float_ptr = ®s[floatReg]; - return *(float *) float_ptr; - } - - case DoubleWidth: - { - uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg]; - void *double_ptr = &double_val; - return *(double *) double_ptr; - } - - default: - panic("Attempted to read a %d bit floating point register!", width); - } -} - -FloatRegBits -FloatRegFile::readRegBits(int floatReg, int width, ThreadID tid) -{ - if (floatReg < NumFloatArchRegs - 1) { - switch(width) - { - case SingleWidth: - return regs[floatReg]; - - case DoubleWidth: - return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg]; - - default: - panic("Attempted to read a %d bit floating point register!", width); - } - } else { - if (width > SingleWidth) - assert("Control Regs are only 32 bits wide"); - - return regs[floatReg]; - } -} - -Fault -FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width, - ThreadID tid) -{ - switch(width) - { - case SingleWidth: - { - float temp = val; - void *float_ptr = &temp; - regs[floatReg] = *(FloatReg32 *) float_ptr; - break; - } - - case DoubleWidth: - { - const void *double_ptr = &val; - FloatReg64 temp_double = *(FloatReg64 *) double_ptr; - regs[floatReg + 1] = bits(temp_double, 63, 32); - regs[floatReg] = bits(temp_double, 31, 0); - break; - } - - default: - panic("Attempted to read a %d bit floating point register!", width); - } - - return NoFault; -} - -Fault -FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width, - ThreadID tid) -{ - switch(width) - { - case SingleWidth: - regs[floatReg] = val; - break; - - case DoubleWidth: - regs[floatReg + 1] = bits(val, 63, 32); - regs[floatReg] = bits(val, 31, 0); - break; - - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return NoFault; -} - -void -FloatRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumFloatRegs); -} - -void -FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumFloatRegs); -} diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh deleted file mode 100644 index afe6701c5..000000000 --- a/src/arch/mips/regfile/float_regfile.hh +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#ifndef __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__ - -#include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -#include "base/misc.hh" -#include "base/bitfield.hh" -#include "sim/faults.hh" - -#include <string> - -class Checkpoint; - -namespace MipsISA -{ - const uint32_t MIPS32_QNAN = 0x7fbfffff; - const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff); - - enum FPControlRegNums { - FIR = NumFloatArchRegs, - FCCR, - FEXR, - FENR, - FCSR - }; - - enum FCSRBits { - Inexact = 1, - Underflow, - Overflow, - DivideByZero, - Invalid, - Unimplemented - }; - - enum FCSRFields { - Flag_Field = 1, - Enable_Field = 6, - Cause_Field = 11 - }; - - const int SingleWidth = 32; - const int SingleBytes = SingleWidth / 4; - - const int DoubleWidth = 64; - const int DoubleBytes = DoubleWidth / 4; - - const int QuadWidth = 128; - const int QuadBytes = QuadWidth / 4; - - class FloatRegFile - { - protected: - FloatReg32 regs[NumFloatRegs]; - - public: - static const int regWidth = SingleWidth; - - void clear(); - double readReg(int floatReg, int width, ThreadID tid = 0); - FloatRegBits readRegBits(int floatReg, int width, ThreadID tid = 0); - Fault setReg(int floatReg, const FloatRegVal &val, int width, - ThreadID tid = 0); - Fault setRegBits(int floatReg, const FloatRegBits &val, int width, - ThreadID tid = 0); - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - }; - -} // namespace MipsISA - -#endif diff --git a/src/arch/mips/regfile/int_regfile.cc b/src/arch/mips/regfile/int_regfile.cc deleted file mode 100644 index 88de4be94..000000000 --- a/src/arch/mips/regfile/int_regfile.cc +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Korey Sewell - * Jaidev Patwardhan - */ - -#include "arch/mips/regfile/int_regfile.hh" -#include "sim/serialize.hh" - -using namespace MipsISA; -using namespace std; - -void -IntRegFile::clear() -{ - bzero(®s, sizeof(regs)); - currShadowSet=0; -} - -int -IntRegFile::readShadowSet() -{ - return currShadowSet; -} - -void -IntRegFile::setShadowSet(int css) -{ - DPRINTF(MipsPRA, "Setting Shadow Set to :%d (%s)\n", css, currShadowSet); - currShadowSet = css; -} - -IntReg -IntRegFile::readReg(int intReg) -{ - if (intReg < NumIntArchRegs) { - // Regular GPR Read - DPRINTF(MipsPRA, "Reading Reg: %d, CurrShadowSet: %d\n", intReg, - currShadowSet); - - return regs[intReg + NumIntArchRegs * currShadowSet]; - } else { - unsigned special_reg_num = intReg - NumIntArchRegs; - - // Read A Special Reg - return regs[TotalArchRegs + special_reg_num]; - } -} - -Fault -IntRegFile::setReg(int intReg, const IntReg &val) -{ - if (intReg != ZeroReg) { - if (intReg < NumIntArchRegs) { - regs[intReg + NumIntArchRegs * currShadowSet] = val; - } else { - unsigned special_reg_num = intReg - NumIntArchRegs; - - regs[TotalArchRegs + special_reg_num] = val; - } - } - - return NoFault; -} - -void -IntRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumIntRegs); -} - -void -IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumIntRegs); -} diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh deleted file mode 100644 index 3c7c8c64c..000000000 --- a/src/arch/mips/regfile/int_regfile.hh +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#ifndef __ARCH_MIPS_REGFILE_INT_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_INT_REGFILE_HH__ - -#include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -#include "base/misc.hh" -#include "base/trace.hh" -#include "sim/faults.hh" - -class Checkpoint; - -namespace MipsISA -{ - enum MiscIntRegNums { - LO = NumIntArchRegs, - HI, - DSPACX0, - DSPLo1, - DSPHi1, - DSPACX1, - DSPLo2, - DSPHi2, - DSPACX2, - DSPLo3, - DSPHi3, - DSPACX3, - DSPControl, - DSPLo0 = LO, - DSPHi0 = HI - }; - - //@TODO: Implementing ShadowSets needs to - //edit this value such that: - //TotalArchRegs = NumIntArchRegs * ShadowSets - const int TotalArchRegs = NumIntArchRegs; - - class IntRegFile - { - protected: - IntReg regs[NumIntRegs]; - int currShadowSet; - public: - void clear(); - int readShadowSet(); - void setShadowSet(int css); - IntReg readReg(int intReg); - Fault setReg(int intReg, const IntReg &val); - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - - }; - -} // namespace MipsISA - -#endif diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc deleted file mode 100644 index 975fad963..000000000 --- a/src/arch/mips/regfile/regfile.cc +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Korey Sewell - */ - -#include "arch/mips/regfile/regfile.hh" -#include "sim/serialize.hh" - -using namespace std; - -namespace MipsISA -{ - -void -RegFile::clear() -{ - intRegFile.clear(); - floatRegFile.clear(); - miscRegFile.clear(); -} - -void -RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes, - BaseCPU *_cpu) -{ - bzero(&intRegFile, sizeof(intRegFile)); - bzero(&floatRegFile, sizeof(floatRegFile)); - miscRegFile.reset(core_name, num_threads, num_vpes, _cpu); -} - -IntReg -RegFile::readIntReg(int intReg) -{ - return intRegFile.readReg(intReg); -} - -Fault -RegFile::setIntReg(int intReg, const IntReg &val) -{ - return intRegFile.setReg(intReg, val); -} - -MiscReg -RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid) -{ - return miscRegFile.readRegNoEffect(miscReg, tid); -} - -MiscReg -RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid) -{ - return miscRegFile.readReg(miscReg, tc, tid); -} - -void -RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid) -{ - miscRegFile.setRegNoEffect(miscReg, val, tid); -} - -void -RegFile::setMiscReg(int miscReg, const MiscReg &val, - ThreadContext *tc, ThreadID tid) -{ - miscRegFile.setReg(miscReg, val, tc, tid); -} - -FloatRegVal -RegFile::readFloatReg(int floatReg) -{ - return floatRegFile.readReg(floatReg,SingleWidth); -} - -FloatRegVal -RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg,width); -} - -FloatRegBits -RegFile::readFloatRegBits(int floatReg) -{ - return floatRegFile.readRegBits(floatReg,SingleWidth); -} - -FloatRegBits -RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg,width); -} - -Fault -RegFile::setFloatReg(int floatReg, const FloatRegVal &val) -{ - return floatRegFile.setReg(floatReg, val, SingleWidth); -} - -Fault -RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width) -{ - return floatRegFile.setReg(floatReg, val, width); -} - -Fault -RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) -{ - return floatRegFile.setRegBits(floatReg, val, SingleWidth); -} - -Fault -RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - return floatRegFile.setRegBits(floatReg, val, width); -} - -void -RegFile::setShadowSet(int css){ - intRegFile.setShadowSet(css); -} - -int -RegFile::instAsid() -{ - return miscRegFile.getInstAsid(); -} - -int -RegFile::dataAsid() -{ - return miscRegFile.getDataAsid(); -} - -Addr -RegFile::readPC() -{ - return pc; -} - -void -RegFile::setPC(Addr val) -{ - pc = val; -} - -Addr -RegFile::readNextPC() -{ - return npc; -} - -void -RegFile::setNextPC(Addr val) -{ - npc = val; -} - -Addr -RegFile::readNextNPC() -{ - return nnpc; -} - -void -RegFile::setNextNPC(Addr val) -{ - nnpc = val; -} - -void -RegFile::serialize(EventManager *em, std::ostream &os) -{ - intRegFile.serialize(os); - //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs); - //SERIALZE_ARRAY(miscRegFile); - //SERIALIZE_SCALAR(miscRegs.fpcr); - //SERIALIZE_SCALAR(miscRegs.lock_flag); - //SERIALIZE_SCALAR(miscRegs.lock_addr); - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - -void -RegFile::unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion) -{ - intRegFile.unserialize(cp, section); - //UNSERIALIZE_ARRAY(floatRegFile); - //UNSERIALZE_ARRAY(miscRegFile); - //UNSERIALIZE_SCALAR(miscRegs.fpcr); - //UNSERIALIZE_SCALAR(miscRegs.lock_flag); - //UNSERIALIZE_SCALAR(miscRegs.lock_addr); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); - -} - -} // namespace MipsISA diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh deleted file mode 100644 index 91951b078..000000000 --- a/src/arch/mips/regfile/regfile.hh +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_REGFILE_HH__ - -#include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -//#include "arch/mips/mt.hh" -#include "arch/mips/regfile/int_regfile.hh" -#include "arch/mips/regfile/float_regfile.hh" -#include "arch/mips/regfile/misc_regfile.hh" -//#include "cpu/base.hh" -#include "sim/faults.hh" - -class BaseCPU; -class Checkpoint; -class EventManager; - -namespace MipsISA -{ - class RegFile { - protected: - Addr pc; // program counter - Addr npc; // next-cycle program counter - Addr nnpc; // next-next-cycle program counter - // used to implement branch delay slot - // not real register - - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file - - public: - void clear(); - void reset(std::string core_name, ThreadID num_threads, - unsigned num_vpes, BaseCPU *_cpu); - MiscRegFile *getMiscRegFilePtr(); - - IntReg readIntReg(int intReg); - Fault setIntReg(int intReg, const IntReg &val); - - - MiscReg readMiscRegNoEffect(int miscReg, ThreadID tid = 0); - MiscReg readMiscReg(int miscReg, ThreadContext *tc, - ThreadID tid = 0); - void setMiscRegNoEffect(int miscReg, const MiscReg &val, - ThreadID tid = 0); - void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext *tc, ThreadID tid = 0); - - FloatRegVal readFloatReg(int floatReg); - FloatRegVal readFloatReg(int floatReg, int width); - FloatRegBits readFloatRegBits(int floatReg); - FloatRegBits readFloatRegBits(int floatReg, int width); - Fault setFloatReg(int floatReg, const FloatRegVal &val); - Fault setFloatReg(int floatReg, const FloatRegVal &val, int width); - Fault setFloatRegBits(int floatReg, const FloatRegBits &val); - Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width); - - - void setShadowSet(int css); - - int instAsid(); - int dataAsid(); - - public: - Addr readPC(); - void setPC(Addr val); - - Addr readNextPC(); - void setNextPC(Addr val); - - Addr readNextNPC(); - void setNextNPC(Addr val); - - void serialize(EventManager *em, std::ostream &os); - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); - - }; - -} // namespace MipsISA - -#endif diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh new file mode 100644 index 000000000..b996b4717 --- /dev/null +++ b/src/arch/mips/registers.hh @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * Copyright (c) 2007 MIPS Technologies, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Korey Sewell + */ + +#ifndef __ARCH_MIPS_REGISTERS_HH__ +#define __ARCH_MIPS_REGISTERS_HH__ + +#include "arch/mips/max_inst_regs.hh" +#include "base/misc.hh" +#include "base/types.hh" + +class ThreadContext; + +namespace MipsISA +{ + +using MipsISAInst::MaxInstSrcRegs; +using MipsISAInst::MaxInstDestRegs; + +// Constants Related to the number of registers +const int NumIntArchRegs = 32; +const int NumIntSpecialRegs = 9; +const int NumFloatArchRegs = 32; +const int NumFloatSpecialRegs = 5; + +const int MaxShadowRegSets = 16; // Maximum number of shadow register sets +const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs +const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// + +const uint32_t MIPS32_QNAN = 0x7fbfffff; +const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff); + +enum FPControlRegNums { + FIR = NumFloatArchRegs, + FCCR, + FEXR, + FENR, + FCSR +}; + +enum FCSRBits { + Inexact = 1, + Underflow, + Overflow, + DivideByZero, + Invalid, + Unimplemented +}; + +enum FCSRFields { + Flag_Field = 1, + Enable_Field = 6, + Cause_Field = 11 +}; + +enum MiscIntRegNums { + LO = NumIntArchRegs, + HI, + DSPACX0, + DSPLo1, + DSPHi1, + DSPACX1, + DSPLo2, + DSPHi2, + DSPACX2, + DSPLo3, + DSPHi3, + DSPACX3, + DSPControl, + DSPLo0 = LO, + DSPHi0 = HI +}; + +// semantically meaningful register indices +const int ZeroReg = 0; +const int AssemblerReg = 1; +const int SyscallSuccessReg = 7; +const int FirstArgumentReg = 4; +const int ReturnValueReg = 2; + +const int KernelReg0 = 26; +const int KernelReg1 = 27; +const int GlobalPointerReg = 28; +const int StackPointerReg = 29; +const int FramePointerReg = 30; +const int ReturnAddressReg = 31; + +const int SyscallPseudoReturnReg = 3; + +//@TODO: Implementing ShadowSets needs to +//edit this value such that: +//TotalArchRegs = NumIntArchRegs * ShadowSets +const int TotalArchRegs = NumIntArchRegs; + +// These help enumerate all the registers for dependence tracking. +const int FP_Base_DepTag = NumIntRegs; +const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; + +// Enumerate names for 'Control' Registers in the CPU +// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 +// (Register Number-Register Select) Summary of Register +//------------------------------------------------------ +// The first set of names classify the CP0 names as Register Banks +// for easy indexing when using the 'RD + SEL' index combination +// in CP0 instructions. +enum MiscRegTags { + Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3 + MVPControl, + MVPConf0, + MVPConf1, + + CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15 + VPEControl, + VPEConf0, + VPEConf1, + YQMask, + VPESchedule, + VPEScheFBack, + VPEOpt, + + EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23 + TCStatus, + TCBind, + TCRestart, + TCHalt, + TCContext, + TCSchedule, + TCScheFBack, + + EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24 + + Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33 + ContextConfig, + + PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41 + PageGrain = Ctrl_Base_DepTag + 41, + + Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55 + SRSConf0, + SRSConf1, + SRSConf2, + SRSConf3, + SRSConf4, + + HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63 + + BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71 + + Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79 + + EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87 + + Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95 + + Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103 + IntCtl, + SRSCtl, + SRSMap, + + Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111 + + EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119 + + PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127, + EBase, + + Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135 + Config1, + Config2, + Config3, + Config4, + Config5, + Config6, + Config7, + + + LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143 + + WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151 + WatchLo1, + WatchLo2, + WatchLo3, + WatchLo4, + WatchLo5, + WatchLo6, + WatchLo7, + + WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159 + WatchHi1, + WatchHi2, + WatchHi3, + WatchHi4, + WatchHi5, + WatchHi6, + WatchHi7, + + XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167 + + //Bank 21: 168-175 + + //Bank 22: 176-183 + + Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191 + TraceControl1, + TraceControl2, + UserTraceData, + TraceBPC, + + DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199 + + PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207 + PerfCnt1, + PerfCnt2, + PerfCnt3, + PerfCnt4, + PerfCnt5, + PerfCnt6, + PerfCnt7, + + ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215 + + CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223 + CacheErr1, + CacheErr2, + CacheErr3, + + TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231 + DataLo1, + TagLo2, + DataLo3, + TagLo4, + DataLo5, + TagLo6, + DataLo7, + + TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239 + DataHi1, + TagHi2, + DataHi3, + TagHi4, + DataHi5, + TagHi6, + DataHi7, + + + ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247 + + DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256 + + LLFlag = Ctrl_Base_DepTag + 257, + + NumControlRegs +}; + +const int TotalDataRegs = NumIntRegs + NumFloatRegs; + +const int NumMiscRegs = NumControlRegs; + +const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; + +typedef uint16_t RegIndex; + +typedef uint32_t IntReg; + +// floating point register file entry type +typedef uint32_t FloatRegBits; +typedef float FloatReg; + +// cop-0/cop-1 system control register +typedef uint64_t MiscReg; + +typedef union { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; +} AnyReg; + +} // namespace MipsISA + +#endif diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 001dc2cb7..18a29122c 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -58,6 +58,21 @@ using namespace MipsISA; #define MODE2MASK(X) (1 << (X)) +static inline mode_type +getOperatingMode(MiscReg Stat) +{ + if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) { + return mode_kernel; + } else if((Stat & 0x18) == 0x8) { + return mode_supervisor; + } else if((Stat & 0x18) == 0x10) { + return mode_user; + } else { + return mode_number; + } +} + + TLB::TLB(const Params *p) : BaseTLB(p), size(p->size), nlu(0) { diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh index 4e0684e78..f203d7d57 100644 --- a/src/arch/mips/types.hh +++ b/src/arch/mips/types.hh @@ -37,29 +37,9 @@ namespace MipsISA { typedef uint32_t MachInst; typedef uint64_t ExtMachInst; - typedef uint16_t RegIndex; - typedef uint32_t IntReg; typedef uint64_t LargestRead; - - // floating point register file entry type - typedef uint32_t FloatReg32; - typedef uint64_t FloatReg64; - typedef uint64_t FloatRegBits; - - typedef double FloatRegVal; - typedef double FloatReg; - - // cop-0/cop-1 system control register - typedef uint64_t MiscReg; - - typedef union { - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - //used in FP convert & round function enum ConvertType{ SINGLE_TO_DOUBLE, diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index 5908caf68..4723d6301 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -233,18 +233,6 @@ isSnan(void *val_ptr, int size) } } -void -copyRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Regs Not Implemented Yet\n"); -} - -void -copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} - template <class CPU> void zeroRegisters(CPU *cpu) @@ -262,4 +250,16 @@ startupCPU(ThreadContext *tc, int cpuId) tc->activate(0/*tc->threadId()*/); } +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + panic("Copy Regs Not Implemented Yet\n"); +} + +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + panic("Copy Misc. Regs Not Implemented Yet\n"); +} + } // namespace MipsISA diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 1c77b6ff2..23c965bd4 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -98,27 +98,11 @@ namespace MipsISA { // // Register File Utility Functions // - static inline int flattenFloatIndex(ThreadContext * tc, int reg) - { - return reg; - } - - static inline int flattenIntIndex(ThreadContext * tc, int reg) - { - // Implement Shadow Sets Stuff Here; - return reg; - } - static inline MachInst makeRegisterCopy(int dest, int src) { panic("makeRegisterCopy not implemented"); return 0; } - void copyRegs(ThreadContext *src, ThreadContext *dest); - - void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - - template <class CPU> void zeroRegisters(CPU *cpu); @@ -139,6 +123,9 @@ namespace MipsISA { // CPU Utility // void startupCPU(ThreadContext *tc, int cpuId); + + void copyRegs(ThreadContext *src, ThreadContext *dest); + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); }; diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 940cf2076..86ccaa010 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -34,11 +34,8 @@ Import('*') if env['TARGET_ISA'] == 'sparc': Source('asi.cc') Source('faults.cc') - Source('floatregfile.cc') - Source('intregfile.cc') - Source('miscregfile.cc') + Source('isa.cc') Source('pagetable.cc') - Source('regfile.cc') Source('remote_gdb.cc') Source('tlb.cc') Source('utility.cc') diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc deleted file mode 100644 index 2d1af2218..000000000 --- a/src/arch/sparc/floatregfile.cc +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/floatregfile.hh" -#include "base/trace.hh" -#include "sim/byteswap.hh" -#include "sim/serialize.hh" - -#include <string.h> - -using namespace SparcISA; -using namespace std; - -class Checkpoint; - -void FloatRegFile::clear() -{ - memset(regSpace, 0, sizeof(regSpace)); -} - -FloatReg FloatRegFile::readReg(int floatReg, int width) -{ - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - FloatReg result; - switch(width) - { - case SingleWidth: - uint32_t result32; - float32_t fresult32; - memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); - result32 = htog(result32); - memcpy(&fresult32, &result32, sizeof(result32)); - result = fresult32; - DPRINTF(FloatRegs, "Read FP32 register %d = [%f]0x%x\n", - floatReg, result, result32); - break; - case DoubleWidth: - uint64_t result64; - float64_t fresult64; - memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); - result64 = htog(result64); - memcpy(&fresult64, &result64, sizeof(result64)); - result = fresult64; - DPRINTF(FloatRegs, "Read FP64 register %d = [%f]0x%x\n", - floatReg, result, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return result; -} - -FloatRegBits FloatRegFile::readRegBits(int floatReg, int width) -{ - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - FloatRegBits result; - switch(width) - { - case SingleWidth: - uint32_t result32; - memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); - result = htog(result32); - DPRINTF(FloatRegs, "Read FP32 bits register %d = 0x%x\n", - floatReg, result); - break; - case DoubleWidth: - uint64_t result64; - memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); - result = htog(result64); - DPRINTF(FloatRegs, "Read FP64 bits register %d = 0x%x\n", - floatReg, result); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return result; -} - -Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width) -{ - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - - uint32_t result32; - uint64_t result64; - float32_t fresult32; - float64_t fresult64; - switch(width) - { - case SingleWidth: - fresult32 = val; - memcpy(&result32, &fresult32, sizeof(result32)); - result32 = gtoh(result32); - memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); - DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n", - floatReg, result32); - break; - case DoubleWidth: - fresult64 = val; - memcpy(&result64, &fresult64, sizeof(result64)); - result64 = gtoh(result64); - memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); - DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n", - floatReg, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return NoFault; -} - -Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width) -{ - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - uint32_t result32; - uint64_t result64; - switch(width) - { - case SingleWidth: - result32 = gtoh((uint32_t)val); - memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); - DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n", - floatReg, result32); - break; - case DoubleWidth: - result64 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); - DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n", - floatReg, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return NoFault; -} - -void FloatRegFile::serialize(std::ostream &os) -{ - uint8_t *float_reg = (uint8_t*)regSpace; - SERIALIZE_ARRAY(float_reg, - SingleWidth / 8 * NumFloatRegs); -} - -void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - uint8_t *float_reg = (uint8_t*)regSpace; - UNSERIALIZE_ARRAY(float_reg, - SingleWidth / 8 * NumFloatRegs); -} - diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index ec930e2b0..353521a39 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -34,6 +34,7 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/registers.hh" #include "cpu/thread_context.hh" #include "params/SparcInterrupts.hh" #include "sim/sim_object.hh" diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc deleted file mode 100644 index 54c30d1cc..000000000 --- a/src/arch/sparc/intregfile.cc +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/intregfile.hh" -#include "base/trace.hh" -#include "base/misc.hh" -#include "sim/serialize.hh" - -#include <string.h> - -using namespace SparcISA; -using namespace std; - -class Checkpoint; - -void IntRegFile::clear() -{ - memset(regs, 0, sizeof(IntReg) * NumIntRegs); -} - -IntRegFile::IntRegFile() -{ - clear(); -} - -IntReg IntRegFile::readReg(int intReg) -{ - DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, regs[intReg]); - return regs[intReg]; -} - -void IntRegFile::setReg(int intReg, const IntReg &val) -{ - if(intReg) - { - DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val); - regs[intReg] = val; - } - return; -} - -void IntRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumIntRegs); - SERIALIZE_ARRAY(microRegs, NumMicroIntRegs); -} - -void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumIntRegs); - UNSERIALIZE_ARRAY(microRegs, NumMicroIntRegs); -} diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/isa.cc index 38eba3862..3226b4e42 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,29 +26,65 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black - * Ali Saidi */ #include "arch/sparc/asi.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/isa.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" -using namespace SparcISA; -using namespace std; - -class Checkpoint; +namespace SparcISA +{ enum RegMask { PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12) }; -void MiscRegFile::clear() +void +ISA::reloadRegMap() +{ + installGlobals(gl, CurrentGlobalsOffset); + installWindow(cwp, CurrentWindowOffset); + // Microcode registers. + for (int i = 0; i < NumMicroIntRegs; i++) + intRegMap[MicroIntOffset + i] = i + TotalGlobals + NWindows * 16; + installGlobals(gl, NextGlobalsOffset); + installWindow(cwp - 1, NextWindowOffset); + installGlobals(gl, PreviousGlobalsOffset); + installWindow(cwp + 1, PreviousWindowOffset); +} + +void +ISA::installWindow(int cwp, int offset) { + assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs); + RegIndex *mapChunk = intRegMap + offset; + for (int i = 0; i < NumWindowedRegs; i++) + mapChunk[i] = TotalGlobals + + ((i - cwp * RegsPerWindow + TotalWindowed) % (TotalWindowed)); +} + +void +ISA::installGlobals(int gl, int offset) +{ + assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs); + RegIndex *mapChunk = intRegMap + offset; + mapChunk[0] = 0; + for (int i = 1; i < NumGlobalRegs; i++) + mapChunk[i] = i + gl * NumGlobalRegs; +} + +void +ISA::clear() +{ + cwp = 0; + gl = 0; + reloadRegMap(); + //y = 0; //ccr = 0; asi = 0; @@ -66,13 +102,11 @@ void MiscRegFile::clear() pstate = 0; tl = 0; pil = 0; - cwp = 0; //cansave = 0; //canrestore = 0; //cleanwin = 0; //otherwin = 0; //wstate = 0; - gl = 0; //In a T1, bit 11 is apparently always 1 hpstate = (1 << 11); memset(htstate, 0, sizeof(htstate)); @@ -96,7 +130,8 @@ void MiscRegFile::clear() #endif } -MiscReg MiscRegFile::readRegNoEffect(int miscReg) +MiscReg +ISA::readMiscRegNoEffect(int miscReg) { // The three miscRegs are moved up from the switch statement @@ -255,7 +290,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) } } -MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) +MiscReg +ISA::readMiscReg(int miscReg, ThreadContext * tc) { switch (miscReg) { // tick and stick are aliased to each other in niagra @@ -311,10 +347,11 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) #endif } - return readRegNoEffect(miscReg); + return readMiscRegNoEffect(miscReg); } -void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val) +void +ISA::setMiscRegNoEffect(int miscReg, MiscReg val) { switch (miscReg) { // case MISCREG_Y: @@ -493,8 +530,8 @@ void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val) } } -void MiscRegFile::setReg(int miscReg, - const MiscReg &val, ThreadContext * tc) +void +ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) { MiscReg new_val = val; @@ -529,8 +566,15 @@ void MiscRegFile::setReg(int miscReg, new_val = val >= NWindows ? NWindows - 1 : val; if (val >= NWindows) new_val = NWindows - 1; + + installWindow(new_val, CurrentWindowOffset); + installWindow(new_val - 1, NextWindowOffset); + installWindow(new_val + 1, PreviousWindowOffset); break; case MISCREG_GL: + installGlobals(val, CurrentGlobalsOffset); + installGlobals(val, NextGlobalsOffset); + installGlobals(val, PreviousGlobalsOffset); break; case MISCREG_PIL: case MISCREG_SOFTINT: @@ -565,11 +609,11 @@ void MiscRegFile::setReg(int miscReg, miscReg, val); #endif } - setRegNoEffect(miscReg, new_val); + setMiscRegNoEffect(miscReg, new_val); } void -MiscRegFile::serialize(EventManager *em, std::ostream &os) +ISA::serialize(EventManager *em, std::ostream &os) { SERIALIZE_SCALAR(asi); SERIALIZE_SCALAR(tick); @@ -647,8 +691,7 @@ MiscRegFile::serialize(EventManager *em, std::ostream &os) } void -MiscRegFile::unserialize(EventManager *em, Checkpoint *cp, - const string §ion) +ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) { UNSERIALIZE_SCALAR(asi); UNSERIALIZE_SCALAR(tick); @@ -668,6 +711,7 @@ MiscRegFile::unserialize(EventManager *em, Checkpoint *cp, UNSERIALIZE_SCALAR(pil); UNSERIALIZE_SCALAR(cwp); UNSERIALIZE_SCALAR(gl); + reloadRegMap(); UNSERIALIZE_SCALAR(hpstate); UNSERIALIZE_ARRAY(htstate,MaxTL); UNSERIALIZE_SCALAR(hintp); @@ -722,3 +766,5 @@ MiscRegFile::unserialize(EventManager *em, Checkpoint *cp, #endif } + +} diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/isa.hh index 9eff7fcac..9b4fd50d0 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,144 +26,26 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black - * Ali Saidi */ -#ifndef __ARCH_SPARC_MISCREGFILE_HH__ -#define __ARCH_SPARC_MISCREGFILE_HH__ +#ifndef __ARCH_SPARC_ISA_HH__ +#define __ARCH_SPARC_ISA_HH__ -#include "arch/sparc/faults.hh" -#include "arch/sparc/isa_traits.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/types.hh" +#include "config/full_system.hh" #include "cpu/cpuevent.hh" #include <string> +#include <ostream> class Checkpoint; +class EventManager; +class ThreadContext; namespace SparcISA { - enum MiscRegIndex - { - /** Ancillary State Registers */ -// MISCREG_Y, -// MISCREG_CCR, - MISCREG_ASI, - MISCREG_TICK, - MISCREG_FPRS, - MISCREG_PCR, - MISCREG_PIC, - MISCREG_GSR, - MISCREG_SOFTINT_SET, - MISCREG_SOFTINT_CLR, - MISCREG_SOFTINT, /* 10 */ - MISCREG_TICK_CMPR, - MISCREG_STICK, - MISCREG_STICK_CMPR, - - /** Privilged Registers */ - MISCREG_TPC, - MISCREG_TNPC, - MISCREG_TSTATE, - MISCREG_TT, - MISCREG_PRIVTICK, - MISCREG_TBA, - MISCREG_PSTATE, /* 20 */ - MISCREG_TL, - MISCREG_PIL, - MISCREG_CWP, -// MISCREG_CANSAVE, -// MISCREG_CANRESTORE, -// MISCREG_CLEANWIN, -// MISCREG_OTHERWIN, -// MISCREG_WSTATE, - MISCREG_GL, - - /** Hyper privileged registers */ - MISCREG_HPSTATE, /* 30 */ - MISCREG_HTSTATE, - MISCREG_HINTP, - MISCREG_HTBA, - MISCREG_HVER, - MISCREG_STRAND_STS_REG, - MISCREG_HSTICK_CMPR, - - /** Floating Point Status Register */ - MISCREG_FSR, - - /** MMU Internal Registers */ - MISCREG_MMU_P_CONTEXT, - MISCREG_MMU_S_CONTEXT, /* 40 */ - MISCREG_MMU_PART_ID, - MISCREG_MMU_LSU_CTRL, - - /** Scratchpad regiscers **/ - MISCREG_SCRATCHPAD_R0, /* 60 */ - MISCREG_SCRATCHPAD_R1, - MISCREG_SCRATCHPAD_R2, - MISCREG_SCRATCHPAD_R3, - MISCREG_SCRATCHPAD_R4, - MISCREG_SCRATCHPAD_R5, - MISCREG_SCRATCHPAD_R6, - MISCREG_SCRATCHPAD_R7, - - /* CPU Queue Registers */ - MISCREG_QUEUE_CPU_MONDO_HEAD, - MISCREG_QUEUE_CPU_MONDO_TAIL, - MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ - MISCREG_QUEUE_DEV_MONDO_TAIL, - MISCREG_QUEUE_RES_ERROR_HEAD, - MISCREG_QUEUE_RES_ERROR_TAIL, - MISCREG_QUEUE_NRES_ERROR_HEAD, - MISCREG_QUEUE_NRES_ERROR_TAIL, - - /* All the data for the TLB packed up in one register. */ - MISCREG_TLB_DATA, - MISCREG_NUMMISCREGS - }; - - struct HPSTATE { - const static uint64_t id = 0x800; // this impl. dependent (id) field m - const static uint64_t ibe = 0x400; - const static uint64_t red = 0x20; - const static uint64_t hpriv = 0x4; - const static uint64_t tlz = 0x1; - }; - - - struct PSTATE { - const static int cle = 0x200; - const static int tle = 0x100; - const static int mm = 0xC0; - const static int pef = 0x10; - const static int am = 0x8; - const static int priv = 0x4; - const static int ie = 0x2; - }; - - struct STS { - const static int st_idle = 0x00; - const static int st_wait = 0x01; - const static int st_halt = 0x02; - const static int st_run = 0x05; - const static int st_spec_run = 0x07; - const static int st_spec_rdy = 0x13; - const static int st_ready = 0x19; - const static int active = 0x01; - const static int speculative = 0x04; - const static int shft_id = 8; - const static int shft_fsm0 = 31; - const static int shft_fsm1 = 26; - const static int shft_fsm2 = 21; - const static int shft_fsm3 = 16; - }; - - - const int NumMiscArchRegs = MISCREG_NUMMISCREGS; - const int NumMiscRegs = MISCREG_NUMMISCREGS; - - // The control registers, broken out into fields - class MiscRegFile + class ISA { private: @@ -245,58 +127,86 @@ namespace SparcISA void processSTickCompare(ThreadContext *tc); void processHSTickCompare(ThreadContext *tc); - typedef CpuEventWrapper<MiscRegFile, - &MiscRegFile::processTickCompare> TickCompareEvent; + typedef CpuEventWrapper<ISA, + &ISA::processTickCompare> TickCompareEvent; TickCompareEvent *tickCompare; - typedef CpuEventWrapper<MiscRegFile, - &MiscRegFile::processSTickCompare> STickCompareEvent; + typedef CpuEventWrapper<ISA, + &ISA::processSTickCompare> STickCompareEvent; STickCompareEvent *sTickCompare; - typedef CpuEventWrapper<MiscRegFile, - &MiscRegFile::processHSTickCompare> HSTickCompareEvent; + typedef CpuEventWrapper<ISA, + &ISA::processHSTickCompare> HSTickCompareEvent; HSTickCompareEvent *hSTickCompare; #endif + + static const int NumGlobalRegs = 8; + static const int NumWindowedRegs = 24; + static const int WindowOverlap = 8; + + static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs; + static const int RegsPerWindow = NumWindowedRegs - WindowOverlap; + static const int TotalWindowed = NWindows * RegsPerWindow; + + enum InstIntRegOffsets { + CurrentGlobalsOffset = 0, + CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs, + MicroIntOffset = CurrentWindowOffset + NumWindowedRegs, + NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs, + NextWindowOffset = NextGlobalsOffset + NumGlobalRegs, + PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs, + PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs, + TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs + }; + + RegIndex intRegMap[TotalInstIntRegs]; + void installWindow(int cwp, int offset); + void installGlobals(int gl, int offset); + void reloadRegMap(); + public: void clear(); - MiscRegFile() - { - clear(); - } + void serialize(EventManager *em, std::ostream & os); - MiscReg readRegNoEffect(int miscReg); + void unserialize(EventManager *em, Checkpoint *cp, + const std::string & section); - MiscReg readReg(int miscReg, ThreadContext *tc); + protected: + + bool isHyperPriv() { return (hpstate & (1 << 2)); } + bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } + bool isNonPriv() { return !isPriv(); } - void setRegNoEffect(int miscReg, const MiscReg &val); + public: - void setReg(int miscReg, - const MiscReg &val, ThreadContext * tc); + MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscReg(int miscReg, ThreadContext *tc); - int getInstAsid() + void setMiscRegNoEffect(int miscReg, const MiscReg val); + void setMiscReg(int miscReg, const MiscReg val, + ThreadContext *tc); + + int + flattenIntIndex(int reg) { - return priContext | (uint32_t)partId << 13; + assert(reg < TotalInstIntRegs); + RegIndex flatIndex = intRegMap[reg]; + assert(flatIndex < NumIntRegs); + return flatIndex; } - int getDataAsid() + int + flattenFloatIndex(int reg) { - return priContext | (uint32_t)partId << 13; + return reg; } - void serialize(EventManager *em, std::ostream & os); - - void unserialize(EventManager *em, Checkpoint *cp, - const std::string & section); - - void copyMiscRegs(ThreadContext * tc); - - protected: - - bool isHyperPriv() { return (hpstate & (1 << 2)); } - bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } - bool isNonPriv() { return !isPriv(); } + ISA() + { + clear(); + } }; } diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 135bd58c3..bc9273ad3 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -40,7 +40,7 @@ output header {{ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "base/condcodes.hh" #include "base/misc.hh" #include "cpu/static_inst.hh" diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 00dadcf3d..2af624d39 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -33,7 +33,6 @@ #define __ARCH_SPARC_ISA_TRAITS_HH__ #include "arch/sparc/types.hh" -#include "arch/sparc/max_inst_regs.hh" #include "arch/sparc/sparc_traits.hh" #include "base/types.hh" #include "config/full_system.hh" @@ -44,14 +43,10 @@ namespace BigEndianGuest {} namespace SparcISA { - class RegFile; - const int MachineBytes = 8; //This makes sure the big endian versions of certain functions are used. using namespace BigEndianGuest; - using SparcISAInst::MaxInstSrcRegs; - using SparcISAInst::MaxInstDestRegs; // SPARC has a delay slot #define ISA_HAS_DELAY_SLOT 1 @@ -59,23 +54,6 @@ namespace SparcISA // SPARC NOP (sethi %(hi(0), g0) const MachInst NoopMachInst = 0x01000000; - // These enumerate all the registers for dependence tracking. - enum DependenceTags { - FP_Base_DepTag = 32*3+9, - Ctrl_Base_DepTag = FP_Base_DepTag + 64 - }; - - // semantically meaningful register indices - const int ZeroReg = 0; // architecturally meaningful - // the rest of these depend on the ABI - const int ReturnAddressReg = 31; // post call, precall is 15 - const int ReturnValueReg = 8; // Post return, 24 is pre-return. - const int StackPointerReg = 14; - const int FramePointerReg = 30; - - // Some OS syscall use a second register (o1) to return a second value - const int SyscallPseudoReturnReg = 9; - //8K. This value is implmentation specific; and should probably //be somewhere else. const int LogVMPageSize = 13; diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc index 28aa1e50c..b39508386 100644 --- a/src/arch/sparc/linux/process.cc +++ b/src/arch/sparc/linux/process.cc @@ -32,7 +32,7 @@ #include "arch/sparc/isa_traits.hh" #include "arch/sparc/linux/process.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/sparc/miscregs.hh b/src/arch/sparc/miscregs.hh new file mode 100644 index 000000000..f7fff6ee0 --- /dev/null +++ b/src/arch/sparc/miscregs.hh @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi + */ + +#ifndef __ARCH_SPARC_MISCREGS_HH__ +#define __ARCH_SPARC_MISCREGS_HH__ + +#include "base/types.hh" + +namespace SparcISA +{ + enum MiscRegIndex + { + /** Ancillary State Registers */ +// MISCREG_Y, +// MISCREG_CCR, + MISCREG_ASI, + MISCREG_TICK, + MISCREG_FPRS, + MISCREG_PCR, + MISCREG_PIC, + MISCREG_GSR, + MISCREG_SOFTINT_SET, + MISCREG_SOFTINT_CLR, + MISCREG_SOFTINT, /* 10 */ + MISCREG_TICK_CMPR, + MISCREG_STICK, + MISCREG_STICK_CMPR, + + /** Privilged Registers */ + MISCREG_TPC, + MISCREG_TNPC, + MISCREG_TSTATE, + MISCREG_TT, + MISCREG_PRIVTICK, + MISCREG_TBA, + MISCREG_PSTATE, /* 20 */ + MISCREG_TL, + MISCREG_PIL, + MISCREG_CWP, +// MISCREG_CANSAVE, +// MISCREG_CANRESTORE, +// MISCREG_CLEANWIN, +// MISCREG_OTHERWIN, +// MISCREG_WSTATE, + MISCREG_GL, + + /** Hyper privileged registers */ + MISCREG_HPSTATE, /* 30 */ + MISCREG_HTSTATE, + MISCREG_HINTP, + MISCREG_HTBA, + MISCREG_HVER, + MISCREG_STRAND_STS_REG, + MISCREG_HSTICK_CMPR, + + /** Floating Point Status Register */ + MISCREG_FSR, + + /** MMU Internal Registers */ + MISCREG_MMU_P_CONTEXT, + MISCREG_MMU_S_CONTEXT, /* 40 */ + MISCREG_MMU_PART_ID, + MISCREG_MMU_LSU_CTRL, + + /** Scratchpad regiscers **/ + MISCREG_SCRATCHPAD_R0, /* 60 */ + MISCREG_SCRATCHPAD_R1, + MISCREG_SCRATCHPAD_R2, + MISCREG_SCRATCHPAD_R3, + MISCREG_SCRATCHPAD_R4, + MISCREG_SCRATCHPAD_R5, + MISCREG_SCRATCHPAD_R6, + MISCREG_SCRATCHPAD_R7, + + /* CPU Queue Registers */ + MISCREG_QUEUE_CPU_MONDO_HEAD, + MISCREG_QUEUE_CPU_MONDO_TAIL, + MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ + MISCREG_QUEUE_DEV_MONDO_TAIL, + MISCREG_QUEUE_RES_ERROR_HEAD, + MISCREG_QUEUE_RES_ERROR_TAIL, + MISCREG_QUEUE_NRES_ERROR_HEAD, + MISCREG_QUEUE_NRES_ERROR_TAIL, + + /* All the data for the TLB packed up in one register. */ + MISCREG_TLB_DATA, + MISCREG_NUMMISCREGS + }; + + struct HPSTATE { + const static uint64_t id = 0x800; // this impl. dependent (id) field m + const static uint64_t ibe = 0x400; + const static uint64_t red = 0x20; + const static uint64_t hpriv = 0x4; + const static uint64_t tlz = 0x1; + }; + + + struct PSTATE { + const static int cle = 0x200; + const static int tle = 0x100; + const static int mm = 0xC0; + const static int pef = 0x10; + const static int am = 0x8; + const static int priv = 0x4; + const static int ie = 0x2; + }; + + struct STS { + const static int st_idle = 0x00; + const static int st_wait = 0x01; + const static int st_halt = 0x02; + const static int st_run = 0x05; + const static int st_spec_run = 0x07; + const static int st_spec_rdy = 0x13; + const static int st_ready = 0x19; + const static int active = 0x01; + const static int speculative = 0x04; + const static int shft_id = 8; + const static int shft_fsm0 = 31; + const static int shft_fsm1 = 26; + const static int shft_fsm2 = 21; + const static int shft_fsm3 = 16; + }; + + + const int NumMiscArchRegs = MISCREG_NUMMISCREGS; + const int NumMiscRegs = MISCREG_NUMMISCREGS; +} + +#endif diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 7775e858e..c4ab4fe79 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -31,7 +31,9 @@ #ifndef __ARCH_SPARC_PREDECODER_HH__ #define __ARCH_SPARC_PREDECODER_HH__ +#include "arch/sparc/registers.hh" #include "arch/sparc/types.hh" +#include "base/bitfield.hh" #include "base/misc.hh" #include "base/types.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 533e385b3..89e853573 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -32,6 +32,7 @@ #include "arch/sparc/asi.hh" #include "arch/sparc/handlers.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/process.hh" #include "arch/sparc/types.hh" #include "base/loader/object_file.hh" @@ -139,7 +140,7 @@ SparcLiveProcess::startup() //tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); tc->setIntReg(NumIntArchRegs + 5, NWindows); //Start with register window 0 - tc->setMiscRegNoEffect(MISCREG_CWP, 0); + tc->setMiscReg(MISCREG_CWP, 0); //Always use spill and fill traps 0 //tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); tc->setIntReg(NumIntArchRegs + 7, 0); diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc deleted file mode 100644 index a88c6c931..000000000 --- a/src/arch/sparc/regfile.cc +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/regfile.hh" -#include "cpu/thread_context.hh" - -class Checkpoint; - -using namespace SparcISA; -using namespace std; - -//RegFile class methods -Addr RegFile::readPC() -{ - return pc; -} - -void RegFile::setPC(Addr val) -{ - pc = val; -} - -Addr RegFile::readNextPC() -{ - return npc; -} - -void RegFile::setNextPC(Addr val) -{ - npc = val; -} - -Addr RegFile::readNextNPC() -{ - return nnpc; -} - -void RegFile::setNextNPC(Addr val) -{ - nnpc = val; -} - -void RegFile::clear() -{ - floatRegFile.clear(); - intRegFile.clear(); - miscRegFile.clear(); -} - -MiscReg RegFile::readMiscRegNoEffect(int miscReg) -{ - return miscRegFile.readRegNoEffect(miscReg); -} - -MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc) -{ - return miscRegFile.readReg(miscReg, tc); -} - -void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val) -{ - miscRegFile.setRegNoEffect(miscReg, val); -} - -void RegFile::setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc) -{ - miscRegFile.setReg(miscReg, val, tc); -} - -FloatReg RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg, width); -} - -FloatReg RegFile::readFloatReg(int floatReg) -{ - //Use the "natural" width of a single float - return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg, width); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg) -{ - //Use the "natural" width of a single float - return floatRegFile.readRegBits(floatReg, - FloatRegFile::SingleWidth); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width) -{ - floatRegFile.setReg(floatReg, val, width); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val) -{ - //Use the "natural" width of a single float - setFloatReg(floatReg, val, FloatRegFile::SingleWidth); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - floatRegFile.setRegBits(floatReg, val, width); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) -{ - //Use the "natural" width of a single float - floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth); -} - -IntReg RegFile::readIntReg(int intReg) -{ - return intRegFile.readReg(intReg); -} - -void RegFile::setIntReg(int intReg, const IntReg &val) -{ - intRegFile.setReg(intReg, val); -} - -int SparcISA::flattenIntIndex(ThreadContext * tc, int reg) -{ - int gl = tc->readMiscRegNoEffect(MISCREG_GL); - int cwp = tc->readMiscRegNoEffect(MISCREG_CWP); - //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp); - int newReg; - //The total number of global registers - int numGlobals = (MaxGL + 1) * 8; - if(reg < 8) - { - //Global register - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else if(reg < NumIntArchRegs) - { - //Regular windowed register - //Put it in the window pointed to by cwp - newReg = numGlobals + - ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16)); - } - else if(reg < NumIntArchRegs + NumMicroIntRegs) - { - //Microcode register - //Displace from the end of the regular registers - newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16; - } - else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs) - { - reg -= (NumIntArchRegs + NumMicroIntRegs); - if(reg < 8) - { - //Global register from the next window - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else - { - //Windowed register from the previous window - //Put it in the window before the one pointed to by cwp - newReg = numGlobals + - ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16)); - } - } - else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs) - { - reg -= (2 * NumIntArchRegs + NumMicroIntRegs); - if(reg < 8) - { - //Global register from the previous window - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else - { - //Windowed register from the next window - //Put it in the window after the one pointed to by cwp - newReg = numGlobals + - ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16)); - } - } - else - panic("Tried to flatten invalid register index %d!\n", reg); - DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg); - return newReg; - //return intRegFile.flattenIndex(reg); -} - -void -RegFile::serialize(EventManager *em, ostream &os) -{ - intRegFile.serialize(os); - floatRegFile.serialize(os); - miscRegFile.serialize(em, os); - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - -void -RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) -{ - intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); - miscRegFile.unserialize(em, cp, section); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); -} - -void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - - uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); - - // Read all the trap level dependent registers and save them off - for(int i = 1; i <= MaxTL; i++) - { - src->setMiscRegNoEffect(MISCREG_TL, i); - dest->setMiscRegNoEffect(MISCREG_TL, i); - - dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); - dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); - dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); - dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); - } - - // Save off the traplevel - dest->setMiscRegNoEffect(MISCREG_TL, tl); - src->setMiscRegNoEffect(MISCREG_TL, tl); - - - // ASRs -// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); -// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); - dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); - dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); - dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); - dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); - dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); - dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); - dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); - - // Priv Registers - dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); - dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); - dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); - dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); - dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); -// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); -// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); -// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); -// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); -// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); - dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); - - // Hyperprivilged registers - dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); - dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); - dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); - dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, - src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); - dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, - src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); - - // FSR - dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); - - //Strand Status Register - dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, - src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); - - // MMU Registers - dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, - src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); - dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, - src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); - dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, - src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); - dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, - src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); - - // Scratchpad Registers - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); - - // Queue Registers - dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); -} - -void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest) -{ - //First loop through the integer registers. - int old_gl = src->readMiscRegNoEffect(MISCREG_GL); - int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); - //Globals - for (int x = 0; x < MaxGL; ++x) { - src->setMiscRegNoEffect(MISCREG_GL, x); - dest->setMiscRegNoEffect(MISCREG_GL, x); - // Skip %g0 which is always zero. - for (int y = 1; y < 8; y++) - dest->setIntReg(y, src->readIntReg(y)); - } - //Locals and ins. Outs are all also ins. - for (int x = 0; x < NWindows; ++x) { - src->setMiscRegNoEffect(MISCREG_CWP, x); - dest->setMiscRegNoEffect(MISCREG_CWP, x); - for (int y = 16; y < 32; y++) - dest->setIntReg(y, src->readIntReg(y)); - } - //Microcode reg and pseudo int regs (misc regs in the integer regfile). - for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) - dest->setIntReg(y, src->readIntReg(y)); - - //Restore src's GL, CWP - src->setMiscRegNoEffect(MISCREG_GL, old_gl); - src->setMiscRegNoEffect(MISCREG_CWP, old_cwp); - - - // Then loop through the floating point registers. - for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { - dest->setFloatRegBits(i, src->readFloatRegBits(i)); - } - - // Copy misc. registers - copyMiscRegs(src, dest); - - - // Lastly copy PC/NPC - dest->setPC(src->readPC()); - dest->setNextPC(src->readNextPC()); - dest->setNextNPC(src->readNextNPC()); -} - diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh deleted file mode 100644 index 7da302eb7..000000000 --- a/src/arch/sparc/regfile.hh +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#ifndef __ARCH_SPARC_REGFILE_HH__ -#define __ARCH_SPARC_REGFILE_HH__ - -#include <string> - -#include "arch/sparc/floatregfile.hh" -#include "arch/sparc/intregfile.hh" -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/miscregfile.hh" -#include "arch/sparc/types.hh" -#include "base/types.hh" - -class Checkpoint; - -namespace SparcISA -{ - class RegFile - { - protected: - Addr pc; // Program Counter - Addr npc; // Next Program Counter - Addr nnpc; - - public: - Addr readPC(); - void setPC(Addr val); - - Addr readNextPC(); - void setNextPC(Addr val); - - Addr readNextNPC(); - void setNextNPC(Addr val); - - protected: - IntRegFile intRegFile; // integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file - - public: - - void clear(); - - MiscReg readMiscRegNoEffect(int miscReg); - - MiscReg readMiscReg(int miscReg, ThreadContext *tc); - - void setMiscRegNoEffect(int miscReg, const MiscReg &val); - - void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc); - - int instAsid() - { - return miscRegFile.getInstAsid(); - } - - int dataAsid() - { - return miscRegFile.getDataAsid(); - } - - FloatReg readFloatReg(int floatReg, int width); - - FloatReg readFloatReg(int floatReg); - - FloatRegBits readFloatRegBits(int floatReg, int width); - - FloatRegBits readFloatRegBits(int floatReg); - - void setFloatReg(int floatReg, const FloatReg &val, int width); - - void setFloatReg(int floatReg, const FloatReg &val); - - void setFloatRegBits(int floatReg, const FloatRegBits &val, int width); - - void setFloatRegBits(int floatReg, const FloatRegBits &val); - - IntReg readIntReg(int intReg); - - void setIntReg(int intReg, const IntReg &val); - - void serialize(EventManager *em, std::ostream &os); - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); - - public: - }; - - int flattenIntIndex(ThreadContext * tc, int reg); - - static inline int - flattenFloatIndex(ThreadContext * tc, int reg) - { - return reg; - } - - void copyRegs(ThreadContext *src, ThreadContext *dest); - - void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - -} // namespace SparcISA - -#endif diff --git a/src/arch/sparc/floatregfile.hh b/src/arch/sparc/registers.hh index 265e71b4a..639b7a487 100644 --- a/src/arch/sparc/floatregfile.hh +++ b/src/arch/sparc/registers.hh @@ -29,58 +29,52 @@ * Ali Saidi */ -#ifndef __ARCH_SPARC_FLOATREGFILE_HH__ -#define __ARCH_SPARC_FLOATREGFILE_HH__ +#ifndef __ARCH_SPARC_REGISTERS_HH__ +#define __ARCH_SPARC_REGISTERS_HH__ -#include "arch/sparc/faults.hh" -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/types.hh" - -#include <string> - -class Checkpoint; +#include "arch/sparc/max_inst_regs.hh" +#include "arch/sparc/miscregs.hh" +#include "arch/sparc/sparc_traits.hh" +#include "base/types.hh" namespace SparcISA { - const int NumFloatArchRegs = 64; - const int NumFloatRegs = 64; - - typedef float float32_t; - typedef double float64_t; - //FIXME long double refers to a 10 byte float, rather than a - //16 byte float as required. This data type may have to be emulated. - typedef double float128_t; - - class FloatRegFile + using SparcISAInst::MaxInstSrcRegs; + using SparcISAInst::MaxInstDestRegs; + + typedef uint64_t IntReg; + typedef uint64_t MiscReg; + typedef float FloatReg; + typedef uint32_t FloatRegBits; + typedef union { - public: - static const int SingleWidth = 32; - static const int DoubleWidth = 64; - static const int QuadWidth = 128; - - protected: + IntReg intReg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; - //Since the floating point registers overlap each other, - //A generic storage space is used. The float to be returned is - //pulled from the appropriate section of this region. - char regSpace[(SingleWidth / 8) * NumFloatRegs]; + typedef uint16_t RegIndex; - public: - - void clear(); - - FloatReg readReg(int floatReg, int width); - - FloatRegBits readRegBits(int floatReg, int width); + // These enumerate all the registers for dependence tracking. + enum DependenceTags { + FP_Base_DepTag = 32*3+9, + Ctrl_Base_DepTag = FP_Base_DepTag + 64 + }; - Fault setReg(int floatReg, const FloatReg &val, int width); + // semantically meaningful register indices + const int ZeroReg = 0; // architecturally meaningful + // the rest of these depend on the ABI + const int ReturnAddressReg = 31; // post call, precall is 15 + const int ReturnValueReg = 8; // Post return, 24 is pre-return. + const int StackPointerReg = 14; + const int FramePointerReg = 30; - Fault setRegBits(int floatReg, const FloatRegBits &val, int width); + // Some OS syscall use a second register (o1) to return a second value + const int SyscallPseudoReturnReg = 9; - void serialize(std::ostream &os); + const int NumIntArchRegs = 32; + const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; - void unserialize(Checkpoint *cp, const std::string §ion); - }; -} +} // namespace SparcISA #endif diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc index 22924736b..eafb488df 100644 --- a/src/arch/sparc/solaris/process.cc +++ b/src/arch/sparc/solaris/process.cc @@ -30,7 +30,7 @@ #include "arch/sparc/isa_traits.hh" #include "arch/sparc/solaris/process.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh index e154ba274..b8e3c2aef 100644 --- a/src/arch/sparc/sparc_traits.hh +++ b/src/arch/sparc/sparc_traits.hh @@ -49,7 +49,8 @@ namespace SparcISA // const int NumIntRegs = // NumRegularIntRegs + // NumMicroIntRegs; -// const int NumFloatRegs = 64; + const int NumFloatRegs = 64; + const int NumFloatArchRegs = NumFloatRegs; // const int NumMiscRegs = 40; } diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 64d73c3c1..1b84a0784 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -31,7 +31,7 @@ #include <cstring> #include "arch/sparc/asi.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/tlb.hh" #include "base/bitfield.hh" #include "base/trace.hh" diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh index 501e2e8cb..70558ec6d 100644 --- a/src/arch/sparc/types.hh +++ b/src/arch/sparc/types.hh @@ -39,19 +39,7 @@ namespace SparcISA typedef uint32_t MachInst; typedef uint64_t ExtMachInst; - typedef uint64_t IntReg; typedef Twin64_t LargestRead; - typedef uint64_t MiscReg; - typedef double FloatReg; - typedef uint64_t FloatRegBits; - typedef union - { - IntReg intReg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - - typedef uint16_t RegIndex; struct CoreSpecific { int core_type; diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index d126d5944..95381db38 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -26,8 +26,9 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "arch/sparc/isa.hh" #include "arch/sparc/kernel_stats.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" @@ -39,7 +40,7 @@ using namespace std; void -MiscRegFile::checkSoftInt(ThreadContext *tc) +ISA::checkSoftInt(ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -84,7 +85,7 @@ getMiscRegName(RegIndex index) } void -MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) +ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -92,18 +93,18 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) switch (miscReg) { /* Full system only ASRs */ case MISCREG_SOFTINT: - setRegNoEffect(miscReg, val);; + setMiscRegNoEffect(miscReg, val);; checkSoftInt(tc); break; case MISCREG_SOFTINT_CLR: - return setReg(MISCREG_SOFTINT, ~val & softint, tc); + return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); case MISCREG_SOFTINT_SET: - return setReg(MISCREG_SOFTINT, val | softint, tc); + return setMiscReg(MISCREG_SOFTINT, val | softint, tc); case MISCREG_TICK_CMPR: if (tickCompare == NULL) tickCompare = new TickCompareEvent(this, tc); - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) cpu->deschedule(tickCompare); time = (tick_cmpr & mask(63)) - (tick & mask(63)); @@ -118,7 +119,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_STICK_CMPR: if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) cpu->deschedule(sTickCompare); time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - @@ -132,10 +133,10 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_PSTATE: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); case MISCREG_PIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); checkSoftInt(tc); break; @@ -143,7 +144,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) panic("Shouldn't be writing HVER\n"); case MISCREG_HINTP: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (hintp) cpu->postInterrupt(IT_HINTP, 0); else @@ -152,12 +153,12 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_HTBA: // clear lower 7 bits on writes. - setRegNoEffect(miscReg, val & ULL(~0x7FFF)); + setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); break; case MISCREG_QUEUE_CPU_MONDO_HEAD: case MISCREG_QUEUE_CPU_MONDO_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (cpu_mondo_head != cpu_mondo_tail) cpu->postInterrupt(IT_CPU_MONDO, 0); else @@ -165,7 +166,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_QUEUE_DEV_MONDO_HEAD: case MISCREG_QUEUE_DEV_MONDO_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (dev_mondo_head != dev_mondo_tail) cpu->postInterrupt(IT_DEV_MONDO, 0); else @@ -173,7 +174,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_QUEUE_RES_ERROR_HEAD: case MISCREG_QUEUE_RES_ERROR_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (res_error_head != res_error_tail) cpu->postInterrupt(IT_RES_ERROR, 0); else @@ -181,14 +182,14 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_QUEUE_NRES_ERROR_HEAD: case MISCREG_QUEUE_NRES_ERROR_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); // This one doesn't have an interrupt to report to the guest OS break; case MISCREG_HSTICK_CMPR: if (hSTickCompare == NULL) hSTickCompare = new HSTickCompareEvent(this, tc); - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) cpu->deschedule(hSTickCompare); time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - @@ -203,7 +204,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_HPSTATE: // T1000 spec says impl. dependent val must always be 1 - setRegNoEffect(miscReg, val | HPSTATE::id); + setMiscRegNoEffect(miscReg, val | HPSTATE::id); #if FULL_SYSTEM if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); @@ -212,13 +213,13 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) #endif break; case MISCREG_HTSTATE: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); break; case MISCREG_STRAND_STS_REG: if (bits(val,2,2)) panic("No support for setting spec_en bit\n"); - setRegNoEffect(miscReg, bits(val,0,0)); + setMiscRegNoEffect(miscReg, bits(val,0,0)); if (!bits(val,0,0)) { DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); // Time to go to sleep @@ -235,7 +236,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) } MiscReg -MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) +ISA::readFSReg(int miscReg, ThreadContext * tc) { uint64_t temp; @@ -257,10 +258,10 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) case MISCREG_HINTP: case MISCREG_HTSTATE: case MISCREG_HSTICK_CMPR: - return readRegNoEffect(miscReg) ; + return readMiscRegNoEffect(miscReg) ; case MISCREG_HTBA: - return readRegNoEffect(miscReg) & ULL(~0x7FFF); + return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF); case MISCREG_HVER: // XXX set to match Legion return ULL(0x3e) << 48 | @@ -275,7 +276,7 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) int x; sys = tc->getSystemPtr(); - temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative); + temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative); // Check that the CPU array is fully populated // (by calling getNumCPus()) assert(sys->numContexts() > tc->contextId()); @@ -309,13 +310,13 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) } void -MiscRegFile::processTickCompare(ThreadContext *tc) +ISA::processTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } void -MiscRegFile::processSTickCompare(ThreadContext *tc) +ISA::processSTickCompare(ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -331,14 +332,14 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) DPRINTF(Timer, "STick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { - setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); + setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); } } else cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1)); } void -MiscRegFile::processHSTickCompare(ThreadContext *tc) +ISA::processHSTickCompare(ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -357,7 +358,7 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { - setReg(MISCREG_HINTP, 1, tc); + setMiscReg(MISCREG_HINTP, 1, tc); } // Need to do something to cause interrupt to happen here !!! @todo } else diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc index d4cc286e6..84e700f6d 100644 --- a/src/arch/sparc/utility.cc +++ b/src/arch/sparc/utility.cc @@ -61,4 +61,159 @@ uint64_t getArgument(ThreadContext *tc, int number, bool fp) { M5_DUMMY_RETURN #endif } + +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + + uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); + + // Read all the trap level dependent registers and save them off + for(int i = 1; i <= MaxTL; i++) + { + src->setMiscRegNoEffect(MISCREG_TL, i); + dest->setMiscRegNoEffect(MISCREG_TL, i); + + dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); + dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); + dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); + dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); + } + + // Save off the traplevel + dest->setMiscRegNoEffect(MISCREG_TL, tl); + src->setMiscRegNoEffect(MISCREG_TL, tl); + + + // ASRs +// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); +// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); + dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); + dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); + dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); + dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); + dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); + dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); + dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); + + // Priv Registers + dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); + dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); + dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); + dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); + dest->setMiscReg(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); +// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); +// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); +// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); +// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); +// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); + dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); + + // Hyperprivilged registers + dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); + dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); + dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); + dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, + src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); + dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, + src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); + + // FSR + dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); + + //Strand Status Register + dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, + src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); + + // MMU Registers + dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, + src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); + dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, + src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); + dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, + src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); + dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, + src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); + + // Scratchpad Registers + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); + + // Queue Registers + dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); +} + +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + //First loop through the integer registers. + int old_gl = src->readMiscRegNoEffect(MISCREG_GL); + int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); + //Globals + for (int x = 0; x < MaxGL; ++x) { + src->setMiscReg(MISCREG_GL, x); + dest->setMiscReg(MISCREG_GL, x); + // Skip %g0 which is always zero. + for (int y = 1; y < 8; y++) + dest->setIntReg(y, src->readIntReg(y)); + } + //Locals and ins. Outs are all also ins. + for (int x = 0; x < NWindows; ++x) { + src->setMiscReg(MISCREG_CWP, x); + dest->setMiscReg(MISCREG_CWP, x); + for (int y = 16; y < 32; y++) + dest->setIntReg(y, src->readIntReg(y)); + } + //Microcode reg and pseudo int regs (misc regs in the integer regfile). + for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) + dest->setIntReg(y, src->readIntReg(y)); + + //Restore src's GL, CWP + src->setMiscReg(MISCREG_GL, old_gl); + src->setMiscReg(MISCREG_CWP, old_cwp); + + + // Then loop through the floating point registers. + for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { + dest->setFloatRegBits(i, src->readFloatRegBits(i)); + } + + // Copy misc. registers + copyMiscRegs(src, dest); + + + // Lastly copy PC/NPC + dest->setPC(src->readPC()); + dest->setNextPC(src->readNextPC()); + dest->setNextNPC(src->readNextNPC()); +} } //namespace SPARC_ISA diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 4ad8950b1..2b9059371 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -33,6 +33,7 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/tlb.hh" #include "base/misc.hh" #include "base/bitfield.hh" @@ -115,6 +116,10 @@ namespace SparcISA #endif } + void copyRegs(ThreadContext *src, ThreadContext *dest); + + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + } // namespace SparcISA #endif diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 4c0460e28..96af0767c 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -88,19 +88,16 @@ Import('*') if env['TARGET_ISA'] == 'x86': Source('cpuid.cc') Source('emulenv.cc') - Source('floatregfile.cc') Source('faults.cc') Source('insts/microfpop.cc') Source('insts/microldstop.cc') Source('insts/microop.cc') Source('insts/microregop.cc') Source('insts/static_inst.cc') - Source('intregfile.cc') - Source('miscregfile.cc') + Source('isa.cc') Source('pagetable.cc') Source('predecoder.cc') Source('predecoder_tables.cc') - Source('regfile.cc') Source('remote_gdb.cc') Source('tlb.cc') Source('utility.cc') diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh index cdb1bf863..bcefd4456 100644 --- a/src/arch/x86/emulenv.hh +++ b/src/arch/x86/emulenv.hh @@ -60,6 +60,7 @@ #include "arch/x86/intregs.hh" #include "arch/x86/segmentregs.hh" +#include "arch/x86/registers.hh" #include "arch/x86/types.hh" namespace X86ISA diff --git a/src/arch/x86/floatregfile.cc b/src/arch/x86/floatregfile.cc deleted file mode 100644 index fce7f4868..000000000 --- a/src/arch/x86/floatregfile.cc +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (c) 2003-2007 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -/* - * Copyright (c) 2007 The Hewlett-Packard Development Company - * All rights reserved. - * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: - * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research & development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/x86/floatregfile.hh" -#include "base/trace.hh" -#include "sim/serialize.hh" - -#include <string.h> - -using namespace X86ISA; -using namespace std; - -class Checkpoint; - -void FloatRegFile::clear() -{ - memset(q, 0, sizeof(FloatReg) * NumFloatRegs); -} - -FloatReg FloatRegFile::readReg(int floatReg, int width) -{ - FloatReg reg = d[floatReg]; - DPRINTF(FloatRegs, "Reading %f from register %d.\n", reg, floatReg); - return reg; -} - -FloatRegBits FloatRegFile::readRegBits(int floatReg, int width) -{ - FloatRegBits reg = q[floatReg]; - DPRINTF(FloatRegs, "Reading %#x from register %d.\n", reg, floatReg); - return reg; -} - -Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width) -{ - DPRINTF(FloatRegs, "Writing %f to register %d.\n", val, floatReg); - d[floatReg] = val; - return NoFault; -} - -Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width) -{ - DPRINTF(FloatRegs, "Writing bits %#x to register %d.\n", val, floatReg); - q[floatReg] = val; - return NoFault; -} - -void FloatRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(q, NumFloatRegs); -} - -void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(q, NumFloatRegs); -} - diff --git a/src/arch/x86/floatregfile.hh b/src/arch/x86/floatregfile.hh deleted file mode 100644 index ab239dd7d..000000000 --- a/src/arch/x86/floatregfile.hh +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2003-2007 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -/* - * Copyright (c) 2007 The Hewlett-Packard Development Company - * All rights reserved. - * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: - * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research & development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_X86_FLOATREGFILE_HH__ -#define __ARCH_X86_FLOATREGFILE_HH__ - -#include <string> - -#include "arch/x86/faults.hh" -#include "arch/x86/types.hh" -#include "arch/x86/x86_traits.hh" - -class Checkpoint; - -namespace X86ISA -{ - //Each 128 bit xmm register is broken into two effective 64 bit registers. - const int NumFloatRegs = - NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; - const int NumFloatArchRegs = NumFloatRegs + 8; - - class FloatRegFile - { - public: - static const int SingleWidth = 32; - static const int DoubleWidth = 64; - static const int QuadWidth = 128; - - protected: - union - { - uint64_t q[NumFloatRegs]; - double d[NumFloatRegs]; - float f[NumFloatRegs][2]; - }; - - public: - void clear(); - - FloatReg readReg(int floatReg, int width); - - FloatRegBits readRegBits(int floatReg, int width); - - Fault setReg(int floatReg, const FloatReg &val, int width); - - Fault setRegBits(int floatReg, const FloatRegBits &val, int width); - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); - }; -} - -#endif //__ARCH_X86_FLOATREGFILE_HH__ diff --git a/src/arch/x86/intregfile.cc b/src/arch/x86/intregfile.cc deleted file mode 100644 index 58a37cb9e..000000000 --- a/src/arch/x86/intregfile.cc +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2003-2007 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -/* - * Copyright (c) 2007 The Hewlett-Packard Development Company - * All rights reserved. - * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: - * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research & development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/x86/intregfile.hh" -#include "base/misc.hh" -#include "base/trace.hh" -#include "sim/serialize.hh" - -#include <string.h> - -using namespace X86ISA; -using namespace std; - -class Checkpoint; - -int IntRegFile::flattenIndex(int reg) -{ - return reg; -} - -void IntRegFile::clear() -{ - memset(regs, 0, sizeof(IntReg) * NumIntRegs); -} - -IntReg IntRegFile::readReg(int intReg) -{ - DPRINTF(IntRegs, "Read int reg %d and got value %#x\n", - intReg, regs[intReg]); - return regs[intReg]; -} - -void IntRegFile::setReg(int intReg, const IntReg &val) -{ - DPRINTF(IntRegs, "Setting int reg %d to value %#x\n", - intReg, val); - regs[intReg] = val; -} - -void IntRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumIntRegs); -} - -void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumIntRegs); -} diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/isa.cc index 317cdadc5..d19a2a6cc 100644 --- a/src/arch/x86/miscregfile.cc +++ b/src/arch/x86/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2006, 2008 The Regents of The University of Michigan + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,76 +28,19 @@ * Authors: Gabe Black */ -/* - * Copyright (c) 2007-2008 The Hewlett-Packard Development Company - * All rights reserved. - * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: - * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research & development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/x86/miscregfile.hh" +#include "arch/x86/floatregs.hh" +#include "arch/x86/isa.hh" #include "arch/x86/tlb.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" #include "sim/serialize.hh" -using namespace X86ISA; -using namespace std; - -class Checkpoint; +namespace X86ISA +{ -void MiscRegFile::updateHandyM5Reg(Efer efer, CR0 cr0, - SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) +void +ISA::updateHandyM5Reg(Efer efer, CR0 cr0, + SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) { HandyM5Reg m5reg; if (efer.lma) { @@ -154,7 +97,8 @@ void MiscRegFile::updateHandyM5Reg(Efer efer, CR0 cr0, regVal[MISCREG_M5_REG] = m5reg; } -void MiscRegFile::clear() +void +ISA::clear() { // Blank everything. 0 might not be an appropriate value for some things, // but it is for most. @@ -163,7 +107,8 @@ void MiscRegFile::clear() regVal[MISCREG_DR7] = 1 << 10; } -MiscReg MiscRegFile::readRegNoEffect(MiscRegIndex miscReg) +MiscReg +ISA::readMiscRegNoEffect(int miscReg) { // Make sure we're not dealing with an illegal control register. // Instructions should filter out these indexes, and nothing else should @@ -177,15 +122,17 @@ MiscReg MiscRegFile::readRegNoEffect(MiscRegIndex miscReg) return regVal[miscReg]; } -MiscReg MiscRegFile::readReg(MiscRegIndex miscReg, ThreadContext * tc) +MiscReg +ISA::readMiscReg(int miscReg, ThreadContext * tc) { if (miscReg == MISCREG_TSC) { return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); } - return readRegNoEffect(miscReg); + return readMiscRegNoEffect(miscReg); } -void MiscRegFile::setRegNoEffect(MiscRegIndex miscReg, const MiscReg &val) +void +ISA::setMiscRegNoEffect(int miscReg, MiscReg val) { // Make sure we're not dealing with an illegal control register. // Instructions should filter out these indexes, and nothing else should @@ -198,8 +145,8 @@ void MiscRegFile::setRegNoEffect(MiscRegIndex miscReg, const MiscReg &val) regVal[miscReg] = val; } -void MiscRegFile::setReg(MiscRegIndex miscReg, - const MiscReg &val, ThreadContext * tc) +void +ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) { MiscReg newVal = val; switch(miscReg) @@ -392,15 +339,41 @@ void MiscRegFile::setReg(MiscRegIndex miscReg, default: break; } - setRegNoEffect(miscReg, newVal); + setMiscRegNoEffect(miscReg, newVal); } -void MiscRegFile::serialize(std::ostream & os) +void +ISA::serialize(EventManager *em, std::ostream & os) { SERIALIZE_ARRAY(regVal, NumMiscRegs); } -void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) +void +ISA::unserialize(EventManager *em, Checkpoint * cp, + const std::string & section) { UNSERIALIZE_ARRAY(regVal, NumMiscRegs); } + +int +ISA::flattenIntIndex(int reg) +{ + //If we need to fold over the index to match byte semantics, do that. + //Otherwise, just strip off any extra bits and pass it through. + if (reg & (1 << 6)) + return (reg & (~(1 << 6) - 0x4)); + else + return (reg & ~(1 << 6)); +} + +int +ISA::flattenFloatIndex(int reg) +{ + if (reg >= NUM_FLOATREGS) { + int top = readMiscRegNoEffect(MISCREG_X87_TOP); + reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top); + } + return reg; +} + +} diff --git a/src/arch/sparc/intregfile.hh b/src/arch/x86/isa.hh index f669f6b0d..285f0aa82 100644 --- a/src/arch/sparc/intregfile.hh +++ b/src/arch/x86/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,44 +26,51 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black - * Ali Saidi */ -#ifndef __ARCH_SPARC_INTREGFILE_HH__ -#define __ARCH_SPARC_INTREGFILE_HH__ +#ifndef __ARCH_X86_ISA_HH__ +#define __ARCH_X86_ISA_HH__ -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/types.hh" -#include "base/bitfield.hh" +#include "arch/x86/miscregs.hh" +#include "arch/x86/registers.hh" +#include "base/types.hh" #include <string> +#include <iostream> class Checkpoint; +class EventManager; +class ThreadContext; -namespace SparcISA +namespace X86ISA { - const int NumIntArchRegs = 32; - const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; - - class IntRegFile + class ISA { protected: - IntReg microRegs[NumMicroIntRegs]; - IntReg regs[NumIntRegs]; + MiscReg regVal[NUM_MISCREGS]; + void updateHandyM5Reg(Efer efer, CR0 cr0, + SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags); public: - void clear(); - IntRegFile(); + ISA() + { + clear(); + } - IntReg readReg(int intReg); + MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscReg(int miscReg, ThreadContext *tc); - void setReg(int intReg, const IntReg &val); + void setMiscRegNoEffect(int miscReg, MiscReg val); + void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc); - void serialize(std::ostream &os); + int flattenIntIndex(int reg); + int flattenFloatIndex(int reg); - void unserialize(Checkpoint *cp, const std::string §ion); + void serialize(EventManager *em, std::ostream &os); + void unserialize(EventManager *em, Checkpoint *cp, + const std::string §ion); }; } diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 8626f117a..3ac9cd4f9 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -103,7 +103,7 @@ output header {{ #include "arch/x86/insts/microregop.hh" #include "arch/x86/insts/static_inst.hh" #include "arch/x86/isa_traits.hh" -#include "arch/x86/regfile.hh" +#include "arch/x86/registers.hh" #include "arch/x86/types.hh" #include "base/misc.hh" #include "cpu/static_inst.hh" @@ -149,6 +149,7 @@ output exec {{ #include <cmath> #include "arch/x86/cpuid.hh" +#include "arch/x86/faults.hh" #include "arch/x86/miscregs.hh" #include "arch/x86/tlb.hh" #include "base/bigint.hh" diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 8203f7c2c..358fe43c8 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py @@ -158,7 +158,7 @@ processCSDescriptor: doPopStackStuffAndCheckRIP: # Check if the RIP is canonical. - sra t7, t1, 47, flags=(EZF,), dataSize=ssz + srai t7, t1, 47, flags=(EZF,), dataSize=ssz # if t7 isn't 0 or -1, it wasn't canonical. br label("doPopStackStuff"), flags=(CEZF,) addi t0, t7, 1, flags=(EZF,), dataSize=ssz diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 2b549bb4a..9f1b7b7c4 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -58,8 +58,6 @@ #ifndef __ARCH_X86_ISATRAITS_HH__ #define __ARCH_X86_ISATRAITS_HH__ -#include "arch/x86/intregs.hh" -#include "arch/x86/max_inst_regs.hh" #include "arch/x86/types.hh" #include "arch/x86/x86_traits.hh" #include "base/types.hh" @@ -73,8 +71,6 @@ namespace X86ISA //This makes sure the little endian version of certain functions //are used. using namespace LittleEndianGuest; - using X86ISAInst::MaxInstSrcRegs; - using X86ISAInst::MaxInstDestRegs; // X86 does not have a delay slot #define ISA_HAS_DELAY_SLOT 0 @@ -83,36 +79,6 @@ namespace X86ISA //XXX This needs to be set to an intermediate instruction struct //which encodes this instruction - // These enumerate all the registers for dependence tracking. - enum DependenceTags { - //There are 16 microcode registers at the moment. This is an - //unusually large constant to make sure there isn't overflow. - FP_Base_DepTag = 128, - Ctrl_Base_DepTag = - FP_Base_DepTag + - //mmx/x87 registers - 8 + - //xmm registers - 16 * 2 + - //The microcode fp registers - 8 + - //The indices that are mapped over the fp stack - 8 - }; - - // semantically meaningful register indices - //There is no such register in X86 - const int ZeroReg = NUM_INTREGS; - const int StackPointerReg = INTREG_RSP; - //X86 doesn't seem to have a link register - const int ReturnAddressReg = 0; - const int ReturnValueReg = INTREG_RAX; - const int FramePointerReg = INTREG_RBP; - - // Some OS syscalls use a second register (rdx) to return a second - // value - const int SyscallPseudoReturnReg = INTREG_RDX; - //4k. This value is not constant on x86. const int LogVMPageSize = 12; const int VMPageSize = (1 << LogVMPageSize); diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc index 1d109ae27..b7d72d594 100644 --- a/src/arch/x86/linux/process.cc +++ b/src/arch/x86/linux/process.cc @@ -57,7 +57,7 @@ #include "arch/x86/isa_traits.hh" #include "arch/x86/linux/process.hh" -#include "arch/x86/regfile.hh" +#include "arch/x86/registers.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh deleted file mode 100644 index 74dcbcbea..000000000 --- a/src/arch/x86/miscregfile.hh +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2003-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -/* - * Copyright (c) 2007-2008 The Hewlett-Packard Development Company - * All rights reserved. - * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: - * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research & development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_X86_MISCREGFILE_HH__ -#define __ARCH_X86_MISCREGFILE_HH__ - -#include <string> - -#include "arch/x86/faults.hh" -#include "arch/x86/miscregs.hh" -#include "arch/x86/types.hh" -#include "base/types.hh" - -class Checkpoint; - -namespace X86ISA -{ - //These will have to be updated in the future. - const int NumMiscArchRegs = NUM_MISCREGS; - const int NumMiscRegs = NUM_MISCREGS; - - class MiscRegFile - { - protected: - MiscReg regVal[NumMiscRegs]; - void updateHandyM5Reg(Efer efer, CR0 cr0, - SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags); - - public: - void clear(); - - MiscRegFile() - { - clear(); - } - - MiscReg readRegNoEffect(MiscRegIndex miscReg); - - MiscReg readReg(MiscRegIndex miscReg, ThreadContext *tc); - - void setRegNoEffect(MiscRegIndex miscReg, const MiscReg &val); - - void setReg(MiscRegIndex miscReg, - const MiscReg &val, ThreadContext *tc); - - void serialize(std::ostream & os); - - void unserialize(Checkpoint * cp, const std::string §ion); - - void copyMiscRegs(ThreadContext * tc); - }; -} - -#endif //__ARCH_X86_MISCREGFILE_HH__ diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index c643a7924..54c7c9121 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -87,6 +87,7 @@ */ #include "arch/x86/isa_traits.hh" +#include "arch/x86/miscregs.hh" #include "arch/x86/process.hh" #include "arch/x86/segmentregs.hh" #include "arch/x86/types.hh" diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc deleted file mode 100644 index 83279902e..000000000 --- a/src/arch/x86/regfile.cc +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2003-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -/* - * Copyright (c) 2007 The Hewlett-Packard Development Company - * All rights reserved. - * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: - * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research & development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/x86/floatregs.hh" -#include "arch/x86/regfile.hh" -#include "base/trace.hh" -#include "sim/serialize.hh" -#include "cpu/thread_context.hh" - -class Checkpoint; - -using namespace X86ISA; -using namespace std; - -//RegFile class methods -Addr RegFile::readPC() -{ - return rip; -} - -void RegFile::setPC(Addr val) -{ - rip = val; -} - -Addr RegFile::readNextPC() -{ - return nextRip; -} - -void RegFile::setNextPC(Addr val) -{ - nextRip = val; -} - -Addr RegFile::readNextNPC() -{ - //There's no way to know how big the -next- instruction will be. - return nextRip + 1; -} - -void RegFile::setNextNPC(Addr val) -{ } - -void RegFile::clear() -{ - floatRegFile.clear(); - intRegFile.clear(); - miscRegFile.clear(); -} - -MiscReg RegFile::readMiscRegNoEffect(int miscReg) -{ - return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg); -} - -MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc) -{ - return miscRegFile.readReg((MiscRegIndex)miscReg, tc); -} - -void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val) -{ - miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val); -} - -void RegFile::setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc) -{ - miscRegFile.setReg((MiscRegIndex)miscReg, val, tc); -} - -FloatReg RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg, width); -} - -FloatReg RegFile::readFloatReg(int floatReg) -{ - //Use the "natural" width of a single float - return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg, width); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg) -{ - //Use the "natural width of a single float - return floatRegFile.readRegBits(floatReg, - FloatRegFile::SingleWidth); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width) -{ - floatRegFile.setReg(floatReg, val, width); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val) -{ - //Use the "natural" width of a single float - setFloatReg(floatReg, val, FloatRegFile::SingleWidth); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - floatRegFile.setRegBits(floatReg, val, width); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) -{ - //Use the "natural" width of a single float - floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth); -} - -IntReg RegFile::readIntReg(int intReg) -{ - return intRegFile.readReg(intReg); -} - -void RegFile::setIntReg(int intReg, const IntReg &val) -{ - intRegFile.setReg(intReg, val); -} - -int X86ISA::flattenIntIndex(ThreadContext * tc, int reg) -{ - //If we need to fold over the index to match byte semantics, do that. - //Otherwise, just strip off any extra bits and pass it through. - if (reg & (1 << 6)) - return (reg & (~(1 << 6) - 0x4)); - else - return (reg & ~(1 << 6)); -} - -int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg) -{ - if (reg >= NUM_FLOATREGS) { - int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP); - reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top); - } - return reg; -} - -void -RegFile::serialize(EventManager *em, std::ostream &os) -{ - intRegFile.serialize(os); - floatRegFile.serialize(os); - miscRegFile.serialize(os); - SERIALIZE_SCALAR(rip); - SERIALIZE_SCALAR(nextRip); -} - -void -RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) -{ - intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); - miscRegFile.unserialize(cp, section); - UNSERIALIZE_SCALAR(rip); - UNSERIALIZE_SCALAR(nextRip); -} - -void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - //panic("copyMiscRegs not implemented for x86!\n"); - warn("copyMiscRegs is naively implemented for x86\n"); - for (int i = 0; i < X86ISA::NumMiscRegs; ++i) { - if ( ( i != MISCREG_CR1 && - !(i > MISCREG_CR4 && i < MISCREG_CR8) && - !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) { - continue; - } - dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); - } - -} - -void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("copyRegs not implemented for x86!\n"); - //copy int regs - //copy float regs - copyMiscRegs(src, dest); - - dest->setPC(src->readPC()); - dest->setNextPC(src->readNextPC()); -} diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh deleted file mode 100644 index 4f285254a..000000000 --- a/src/arch/x86/regfile.hh +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2007 The Hewlett-Packard Development Company - * All rights reserved. - * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: - * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research & development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_X86_REGFILE_HH__ -#define __ARCH_X86_REGFILE_HH__ - -#include <string> - -#include "arch/x86/floatregfile.hh" -#include "arch/x86/intregfile.hh" -#include "arch/x86/isa_traits.hh" -#include "arch/x86/miscregfile.hh" -#include "arch/x86/types.hh" -#include "base/types.hh" - -class Checkpoint; -class EventManager; - -namespace X86ISA -{ - class RegFile - { - protected: - Addr rip; //Program Counter - Addr nextRip; //Next Program Counter - - public: - Addr readPC(); - void setPC(Addr val); - - Addr readNextPC(); - void setNextPC(Addr val); - - Addr readNextNPC(); - void setNextNPC(Addr val); - - protected: - IntRegFile intRegFile; // integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file - - public: - - void clear(); - - MiscReg readMiscRegNoEffect(int miscReg); - - MiscReg readMiscReg(int miscReg, ThreadContext *tc); - - void setMiscRegNoEffect(int miscReg, const MiscReg &val); - - void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc); - - int instAsid() - { - //XXX This doesn't make sense in x86 - return 0; - } - - int dataAsid() - { - //XXX This doesn't make sense in x86 - return 0; - } - - FloatReg readFloatReg(int floatReg, int width); - - FloatReg readFloatReg(int floatReg); - - FloatRegBits readFloatRegBits(int floatReg, int width); - - FloatRegBits readFloatRegBits(int floatReg); - - void setFloatReg(int floatReg, const FloatReg &val, int width); - - void setFloatReg(int floatReg, const FloatReg &val); - - void setFloatRegBits(int floatReg, const FloatRegBits &val, int width); - - void setFloatRegBits(int floatReg, const FloatRegBits &val); - - IntReg readIntReg(int intReg); - - void setIntReg(int intReg, const IntReg &val); - - void serialize(EventManager *em, std::ostream &os); - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); - - public: - }; - - int flattenIntIndex(ThreadContext * tc, int reg); - - int flattenFloatIndex(ThreadContext * tc, int reg); - - void copyRegs(ThreadContext *src, ThreadContext *dest); - - void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - - int InterruptLevel(uint64_t softint); - -}; // namespace X86ISA - -#endif // __ARCH_X86_REGFILE_HH__ diff --git a/src/arch/x86/intregfile.hh b/src/arch/x86/registers.hh index 131245352..e221c4a81 100644 --- a/src/arch/x86/intregfile.hh +++ b/src/arch/x86/registers.hh @@ -1,34 +1,4 @@ /* - * Copyright (c) 2003-2007 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -/* * Copyright (c) 2007 The Hewlett-Packard Development Company * All rights reserved. * @@ -85,45 +55,79 @@ * Authors: Gabe Black */ -#ifndef __ARCH_X86_INTREGFILE_HH__ -#define __ARCH_X86_INTREGFILE_HH__ +#ifndef __ARCH_X86_REGISTERS_HH__ +#define __ARCH_X86_REGISTERS_HH__ #include "arch/x86/intregs.hh" -#include "arch/x86/types.hh" +#include "arch/x86/max_inst_regs.hh" +#include "arch/x86/miscregs.hh" #include "arch/x86/x86_traits.hh" -#include <string> - -class Checkpoint; - namespace X86ISA { - class Regfile; - - const int NumIntArchRegs = NUM_INTREGS; - const int NumIntRegs = - NumIntArchRegs + NumMicroIntRegs + - NumPseudoIntRegs + NumImplicitIntRegs; - - class IntRegFile - { - protected: - IntReg regs[NumIntRegs]; - - public: - - int flattenIndex(int reg); - - void clear(); - - IntReg readReg(int intReg); - - void setReg(int intReg, const IntReg &val); +using X86ISAInst::MaxInstSrcRegs; +using X86ISAInst::MaxInstDestRegs; +const int NumMiscArchRegs = NUM_MISCREGS; +const int NumMiscRegs = NUM_MISCREGS; + +const int NumIntArchRegs = NUM_INTREGS; +const int NumIntRegs = + NumIntArchRegs + NumMicroIntRegs + + NumPseudoIntRegs + NumImplicitIntRegs; + +//Each 128 bit xmm register is broken into two effective 64 bit registers. +const int NumFloatRegs = + NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; +const int NumFloatArchRegs = NumFloatRegs + 8; + +// These enumerate all the registers for dependence tracking. +enum DependenceTags { + //There are 16 microcode registers at the moment. This is an + //unusually large constant to make sure there isn't overflow. + FP_Base_DepTag = 128, + Ctrl_Base_DepTag = + FP_Base_DepTag + + //mmx/x87 registers + 8 + + //xmm registers + 16 * 2 + + //The microcode fp registers + 8 + + //The indices that are mapped over the fp stack + 8 +}; + +// semantically meaningful register indices +//There is no such register in X86 +const int ZeroReg = NUM_INTREGS; +const int StackPointerReg = INTREG_RSP; +//X86 doesn't seem to have a link register +const int ReturnAddressReg = 0; +const int ReturnValueReg = INTREG_RAX; +const int FramePointerReg = INTREG_RBP; + +// Some OS syscalls use a second register (rdx) to return a second +// value +const int SyscallPseudoReturnReg = INTREG_RDX; + +typedef uint64_t IntReg; +//XXX Should this be a 128 bit structure for XMM memory ops? +typedef uint64_t LargestRead; +typedef uint64_t MiscReg; + +//These floating point types are correct for mmx, but not +//technically for x87 (80 bits) or at all for xmm (128 bits) +typedef double FloatReg; +typedef uint64_t FloatRegBits; +typedef union +{ + IntReg intReg; + FloatReg fpReg; + MiscReg ctrlReg; +} AnyReg; - void serialize(std::ostream &os); +typedef uint16_t RegIndex; - void unserialize(Checkpoint *cp, const std::string §ion); - }; -} +}; // namespace X86ISA -#endif //__ARCH_X86_INTREGFILE__ +#endif // __ARCH_X86_REGFILE_HH__ diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 1478c3e66..418f6ffb2 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -59,7 +59,9 @@ #include "config/full_system.hh" +#include "arch/x86/faults.hh" #include "arch/x86/insts/microldstop.hh" +#include "arch/x86/miscregs.hh" #include "arch/x86/pagetable.hh" #include "arch/x86/tlb.hh" #include "arch/x86/x86_traits.hh" diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index c06d664eb..bdf3a814e 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -230,24 +230,6 @@ namespace X86ISA return true; } - typedef uint64_t IntReg; - //XXX Should this be a 128 bit structure for XMM memory ops? - typedef uint64_t LargestRead; - typedef uint64_t MiscReg; - - //These floating point types are correct for mmx, but not - //technically for x87 (80 bits) or at all for xmm (128 bits) - typedef double FloatReg; - typedef uint64_t FloatRegBits; - typedef union - { - IntReg intReg; - FloatReg fpReg; - MiscReg ctrlReg; - } AnyReg; - - typedef uint16_t RegIndex; - struct CoreSpecific { int core_type; }; diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index 9e96b654d..802328db1 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -225,4 +225,30 @@ void startupCPU(ThreadContext *tc, int cpuId) #endif } +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + warn("copyMiscRegs is naively implemented for x86\n"); + for (int i = 0; i < NUM_MISCREGS; ++i) { + if ( ( i != MISCREG_CR1 && + !(i > MISCREG_CR4 && i < MISCREG_CR8) && + !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) { + continue; + } + dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); + } +} + +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + panic("copyRegs not implemented for x86!\n"); + //copy int regs + //copy float regs + copyMiscRegs(src, dest); + + dest->setPC(src->readPC()); + dest->setNextPC(src->readNextPC()); +} + } //namespace X86_ISA diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 9290dc024..d305e2599 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -58,6 +58,7 @@ #ifndef __ARCH_X86_UTILITY_HH__ #define __ARCH_X86_UTILITY_HH__ +#include "arch/x86/miscregs.hh" #include "arch/x86/types.hh" #include "base/hashmap.hh" #include "base/misc.hh" @@ -153,6 +154,10 @@ namespace X86ISA #endif void startupCPU(ThreadContext *tc, int cpuId); + + void copyRegs(ThreadContext *src, ThreadContext *dest); + + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); }; #endif // __ARCH_X86_UTILITY_HH__ diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index fda0528ad..7dacc58ff 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -72,8 +72,7 @@ CheckerCPU::CheckerCPU(Params *p) systemPtr = NULL; #else process = p->process; - thread = new SimpleThread(this, /* thread_num */ 0, process, - /* asid */ 0); + thread = new SimpleThread(this, /* thread_num */ 0, process); tc = thread->getTC(); threadContexts.push_back(tc); diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 3b378700e..450ce6228 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -211,25 +211,12 @@ class CheckerCPU : public BaseCPU return thread->readIntReg(si->srcRegIdx(idx)); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return thread->readFloatReg(reg_idx, width); - } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatReg(reg_idx); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return thread->readFloatRegBits(reg_idx, width); - } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; @@ -242,21 +229,6 @@ class CheckerCPU : public BaseCPU result.integer = val; } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - thread->setFloatReg(reg_idx, val, width); - switch(width) { - case 32: - result.dbl = (double)val; - break; - case 64: - result.dbl = val; - break; - }; - } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; @@ -265,14 +237,6 @@ class CheckerCPU : public BaseCPU } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - thread->setFloatRegBits(reg_idx, val, width); - result.integer = val; - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 2176c597a..d38bd2915 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -174,15 +174,9 @@ class CheckerThreadContext : public ThreadContext uint64_t readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } - FloatReg readFloatReg(int reg_idx, int width) - { return actualTC->readFloatReg(reg_idx, width); } - FloatReg readFloatReg(int reg_idx) { return actualTC->readFloatReg(reg_idx); } - FloatRegBits readFloatRegBits(int reg_idx, int width) - { return actualTC->readFloatRegBits(reg_idx, width); } - FloatRegBits readFloatRegBits(int reg_idx) { return actualTC->readFloatRegBits(reg_idx); } @@ -192,24 +186,12 @@ class CheckerThreadContext : public ThreadContext checkerTC->setIntReg(reg_idx, val); } - void setFloatReg(int reg_idx, FloatReg val, int width) - { - actualTC->setFloatReg(reg_idx, val, width); - checkerTC->setFloatReg(reg_idx, val, width); - } - void setFloatReg(int reg_idx, FloatReg val) { actualTC->setFloatReg(reg_idx, val); checkerTC->setFloatReg(reg_idx, val); } - void setFloatRegBits(int reg_idx, FloatRegBits val, int width) - { - actualTC->setFloatRegBits(reg_idx, val, width); - checkerTC->setFloatRegBits(reg_idx, val, width); - } - void setFloatRegBits(int reg_idx, FloatRegBits val) { actualTC->setFloatRegBits(reg_idx, val); diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 2b9fe4bcf..3d07e95f3 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -50,17 +50,9 @@ class ExecContext { /** Reads an integer register. */ uint64_t readIntRegOperand(const StaticInst *si, int idx); - /** Reads a floating point register of a specific width. */ - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width); - /** Reads a floating point register of single register width. */ FloatReg readFloatRegOperand(const StaticInst *si, int idx); - /** Reads a floating point register of a specific width in its - * binary format, instead of by value. */ - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width); - /** Reads a floating point register in its binary format, instead * of by value. */ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); @@ -68,18 +60,9 @@ class ExecContext { /** Sets an integer register to a value. */ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); - /** Sets a floating point register of a specific width to a value. */ - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width); - /** Sets a floating point register of single width to a value. */ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); - /** Sets the bits of a floating point register of a specific width - * to a binary value. */ - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width); - /** Sets the bits of a floating point register of single width * to a binary value. */ void setFloatRegOperandBits(const StaticInst *si, int idx, diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 3d7d713e8..a2367db63 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -168,7 +168,6 @@ InOrderCPU::InOrderCPU(Params *params) coreType("default"), _status(Idle), tickEvent(this), - miscRegFile(this), timeBuffer(2 , 2), removeInstsThisCycle(false), activityRec(params->name, NumStages, 10, params->activity), @@ -208,12 +207,12 @@ InOrderCPU::InOrderCPU(Params *params) DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n", tid, this->thread[tid]); this->thread[tid] = - new Thread(this, tid, params->workload[tid], tid); + new Thread(this, tid, params->workload[tid]); } else { //Allocate Empty thread so M5 can use later //when scheduling threads to CPU Process* dummy_proc = params->workload[0]; - this->thread[tid] = new Thread(this, tid, dummy_proc, tid); + this->thread[tid] = new Thread(this, tid, dummy_proc); } // Setup the TC that will serve as the interface to the threads/CPU. @@ -265,17 +264,13 @@ InOrderCPU::InOrderCPU(Params *params) squashSeqNum[tid] = MaxAddr; lastSquashCycle[tid] = 0; - intRegFile[tid].clear(); - floatRegFile[tid].clear(); - } + memset(intRegs[tid], 0, sizeof(intRegs[tid])); + memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid])); + isa[tid].clear(); - // Update miscRegFile if necessary - if (numThreads > 1) { - miscRegFile.expandForMultithreading(numThreads, numVirtProcs); + isa[tid].expandForMultithreading(numThreads, numVirtProcs); } - miscRegFile.clear(); - lastRunningCycle = curTick; contextSwitch = false; @@ -461,7 +456,10 @@ InOrderCPU::readFunctional(Addr addr, uint32_t &buffer) void InOrderCPU::reset() { - miscRegFile.reset(coreType, numThreads, numVirtProcs, dynamic_cast<BaseCPU*>(this)); + for (int i = 0; i < numThreads; i++) { + isa[i].reset(coreType, numThreads, + numVirtProcs, dynamic_cast<BaseCPU*>(this)); + } } Port* @@ -888,41 +886,39 @@ InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid) uint64_t InOrderCPU::readIntReg(int reg_idx, ThreadID tid) { - return intRegFile[tid].readReg(reg_idx); + return intRegs[tid][reg_idx]; } FloatReg -InOrderCPU::readFloatReg(int reg_idx, ThreadID tid, int width) +InOrderCPU::readFloatReg(int reg_idx, ThreadID tid) { - - return floatRegFile[tid].readReg(reg_idx, width); + return floatRegs.f[tid][reg_idx]; } FloatRegBits -InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid, int width) +InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid) {; - return floatRegFile[tid].readRegBits(reg_idx, width); + return floatRegs.i[tid][reg_idx]; } void InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid) { - intRegFile[tid].setReg(reg_idx, val); + intRegs[tid][reg_idx] = val; } void -InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid, int width) +InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid) { - floatRegFile[tid].setReg(reg_idx, val, width); + floatRegs.f[tid][reg_idx] = val; } void -InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid, - int width) +InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid) { - floatRegFile[tid].setRegBits(reg_idx, val, width); + floatRegs.i[tid][reg_idx] = val; } uint64_t @@ -966,25 +962,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val, MiscReg InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - return miscRegFile.readRegNoEffect(misc_reg, tid); + return isa[tid].readMiscRegNoEffect(misc_reg); } MiscReg InOrderCPU::readMiscReg(int misc_reg, ThreadID tid) { - return miscRegFile.readReg(misc_reg, tcBase(tid), tid); + return isa[tid].readMiscReg(misc_reg, tcBase(tid)); } void InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) { - miscRegFile.setRegNoEffect(misc_reg, val, tid); + isa[tid].setMiscRegNoEffect(misc_reg, val); } void InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid) { - miscRegFile.setReg(misc_reg, val, tcBase(tid), tid); + isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); } diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 794d81def..75d77c818 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -39,6 +39,7 @@ #include <vector> #include "arch/isa_traits.hh" +#include "arch/types.hh" #include "base/statistics.hh" #include "base/timebuf.hh" #include "base/types.hh" @@ -77,7 +78,6 @@ class InOrderCPU : public BaseCPU typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::MiscReg MiscReg; - typedef TheISA::RegFile RegFile; //DynInstPtr TypeDefs typedef ThePipeline::DynInstPtr DynInstPtr; @@ -257,9 +257,14 @@ class InOrderCPU : public BaseCPU TheISA::IntReg nextNPC[ThePipeline::MaxThreads]; /** The Register File for the CPU */ - TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];; - TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];; - TheISA::MiscRegFile miscRegFile; + union { + FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; + FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; + } floatRegs; + TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs]; + + /** ISA state */ + TheISA::ISA isa[ThePipeline::MaxThreads]; /** Dependency Tracker for Integer & Floating Point Regs */ RegDepMap archRegDepMap[ThePipeline::MaxThreads]; @@ -390,30 +395,18 @@ class InOrderCPU : public BaseCPU return cpuEventNum++; } - /** Get instruction asid. */ - int getInstAsid(ThreadID tid) - { return thread[tid]->getInstAsid(); } - - /** Get data asid. */ - int getDataAsid(ThreadID tid) - { return thread[tid]->getDataAsid(); } - /** Register file accessors */ uint64_t readIntReg(int reg_idx, ThreadID tid); - FloatReg readFloatReg(int reg_idx, ThreadID tid, - int width = TheISA::SingleWidth); + FloatReg readFloatReg(int reg_idx, ThreadID tid); - FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid, - int width = TheISA::SingleWidth); + FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid); void setIntReg(int reg_idx, uint64_t val, ThreadID tid); - void setFloatReg(int reg_idx, FloatReg val, ThreadID tid, - int width = TheISA::SingleWidth); + void setFloatReg(int reg_idx, FloatReg val, ThreadID tid); - void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid, - int width = TheISA::SingleWidth); + void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid); /** Reads a miscellaneous register. */ MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index ee2e5500e..a6abb28b2 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -366,14 +366,9 @@ InOrderDynInst::setIntSrc(int idx, uint64_t val) /** Records an fp register being set to a value. */ void -InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width) +InOrderDynInst::setFloatSrc(int idx, FloatReg val) { - if (width == 32) - instSrc[idx].dbl = val; - else if (width == 64) - instSrc[idx].dbl = val; - else - panic("Unsupported width!"); + instSrc[idx].dbl = val; } /** Records an fp register being set to an integer value. */ @@ -394,22 +389,15 @@ InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid) /** Reads a FP register. */ FloatReg -InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width) -{ - if (width == 32) - return (float)instSrc[idx].dbl; - else if (width == 64) - return instSrc[idx].dbl; - else { - panic("Unsupported Floating Point Width!"); - return 0; - } +InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx) +{ + return instSrc[idx].dbl; } /** Reads a FP register as a integer. */ FloatRegBits -InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx, int width) +InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx) { return instSrc[idx].integer; } @@ -507,31 +495,22 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val) /** Sets a FP register. */ void -InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width) -{ - if (width == 32) { - instResult[idx].val.dbl = (float)val; - instResult[idx].type = Float; - } else if (width == 64) { - instResult[idx].val.dbl = val; - instResult[idx].type = Double; - } else { - panic("Unsupported Floating Point Width!"); - } +InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) +{ + instResult[idx].val.dbl = val; + instResult[idx].type = Float; instResult[idx].tick = curTick; - instResult[idx].width = width; } /** Sets a FP register as a integer. */ void InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + FloatRegBits val) { instResult[idx].type = Integer; instResult[idx].val.integer = val; instResult[idx].tick = curTick; - instResult[idx].width = width; } /** Sets a misc. register. */ diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index 031d882ee..e95a6d039 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -243,10 +243,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted ResultType type; InstValue val; Tick tick; - int width; InstResult() - : type(None), tick(0), width(0) + : type(None), tick(0) {} }; @@ -817,7 +816,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Functions that sets an integer or floating point * source register to a value. */ void setIntSrc(int idx, uint64_t val); - void setFloatSrc(int idx, FloatReg val, int width = 32); + void setFloatSrc(int idx, FloatReg val); void setFloatRegBitsSrc(int idx, uint64_t val); uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; } @@ -830,10 +829,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted * the source reg. value is set using the setSrcReg() function. */ IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0); - FloatReg readFloatRegOperand(const StaticInst *si, int idx, - int width = TheISA::SingleWidth); - TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width = TheISA::SingleWidth); + FloatReg readFloatRegOperand(const StaticInst *si, int idx); + TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); MiscReg readMiscReg(int misc_reg); MiscReg readMiscRegNoEffect(int misc_reg); MiscReg readMiscRegOperand(const StaticInst *si, int idx); @@ -853,15 +850,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Depending on type, return Float or Double */ double readFloatResult(int idx) { - //Should this function have a parameter for what width of return?x - return (instResult[idx].type == Float) ? - (float) instResult[idx].val.dbl : instResult[idx].val.dbl; - } - - double readDoubleResult(int idx) - { - assert(instResult[idx].type == Double); - return instResult[idx].val.dbl; + return instResult[idx].val.dbl; } Tick readResultTime(int idx) { return instResult[idx].tick; } @@ -872,10 +861,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted * it's destination register. */ void setIntRegOperand(const StaticInst *si, int idx, IntReg val); - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width = TheISA::SingleWidth); - void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val, - int width = TheISA::SingleWidth); + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); + void setFloatRegOperandBits(const StaticInst *si, int idx, + TheISA::FloatRegBits val); void setMiscReg(int misc_reg, const MiscReg &val); void setMiscRegNoEffect(int misc_reg, const MiscReg &val); void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val); diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc index c9072b5d5..6c44e2456 100644 --- a/src/cpu/inorder/resources/execution_unit.cc +++ b/src/cpu/inorder/resources/execution_unit.cc @@ -179,8 +179,7 @@ ExecutionUnit::execute(int slot_num) DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n", inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ? - inst->readFloatResult(0) : (inst->resultType(0) == InOrderDynInst::Double) ? - inst->readDoubleResult(0) : inst->readIntResult(0)); + inst->readFloatResult(0) : inst->readIntResult(0)); exec_req->done(); } else { diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc index b30a3a1bf..2f1652c08 100644 --- a/src/cpu/inorder/resources/use_def.cc +++ b/src/cpu/inorder/resources/use_def.cc @@ -53,8 +53,6 @@ UseDefUnit::UseDefUnit(string res_name, int res_id, int res_width, outWriteSeqNum[tid] = maxSeqNum; regDepMap[tid] = &cpu->archRegDepMap[tid]; - - floatRegSize[tid] = cpu->floatRegFile[tid].regWidth; } } @@ -138,12 +136,11 @@ UseDefUnit::execute(int slot_idx) DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File:%x (%08f).\n", tid, reg_idx, - cpu->readFloatRegBits(reg_idx, inst->readTid(), floatRegSize[tid]), - cpu->readFloatReg(reg_idx, inst->readTid(),floatRegSize[tid])); + cpu->readFloatRegBits(reg_idx, inst->readTid()), + cpu->readFloatReg(reg_idx, inst->readTid())); inst->setFloatSrc(ud_idx, - cpu->readFloatReg(reg_idx, inst->readTid(), floatRegSize[tid]), - floatRegSize[tid]); + cpu->readFloatReg(reg_idx, inst->readTid())); } else { reg_idx -= Ctrl_Base_DepTag; DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File:%i.\n", @@ -183,8 +180,7 @@ UseDefUnit::execute(int slot_idx) tid, forward_inst->readFloatResult(dest_reg_idx) , forward_inst->seqNum, inst->seqNum, ud_idx); inst->setFloatSrc(ud_idx, - forward_inst->readFloatResult(dest_reg_idx), - floatRegSize[tid]); + forward_inst->readFloatResult(dest_reg_idx)); } else { DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest. reg value 0x%x from " "[sn:%i] to [sn:%i] source #%i.\n", @@ -244,24 +240,21 @@ UseDefUnit::execute(int slot_idx) cpu->setFloatRegBits(reg_idx, // Check for FloatRegBits Here inst->readIntResult(ud_idx), - inst->readTid(), - floatRegSize[tid]); + inst->readTid()); } else if (inst->resultType(ud_idx) == InOrderDynInst::Float) { DPRINTF(InOrderUseDef, "[tid:%i]: Writing Float Result 0x%x (bits:0x%x) to register idx %i.\n", tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx); cpu->setFloatReg(reg_idx, inst->readFloatResult(ud_idx), - inst->readTid(), - floatRegSize[tid]); + inst->readTid()); } else if (inst->resultType(ud_idx) == InOrderDynInst::Double) { DPRINTF(InOrderUseDef, "[tid:%i]: Writing Double Result 0x%x (bits:0x%x) to register idx %i.\n", tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx); cpu->setFloatReg(reg_idx, // Check for FloatRegBits Here - inst->readDoubleResult(ud_idx), - inst->readTid(), - floatRegSize[tid]); + inst->readFloatResult(ud_idx), + inst->readTid()); } else { panic("Result Type Not Set For [sn:%i] %s.\n", inst->seqNum, inst->instName()); } diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc index a1e9b5948..fe1a0faa1 100644 --- a/src/cpu/inorder/thread_context.cc +++ b/src/cpu/inorder/thread_context.cc @@ -151,24 +151,12 @@ InOrderThreadContext::readIntReg(int reg_idx) } FloatReg -InOrderThreadContext::readFloatReg(int reg_idx, int width) -{ - return cpu->readFloatReg(reg_idx, thread->readTid(), width); -} - -FloatReg InOrderThreadContext::readFloatReg(int reg_idx) { return cpu->readFloatReg(reg_idx, thread->readTid()); } FloatRegBits -InOrderThreadContext::readFloatRegBits(int reg_idx, int width) -{ - return cpu->readFloatRegBits(reg_idx, thread->readTid(), width); -} - -FloatRegBits InOrderThreadContext::readFloatRegBits(int reg_idx) { return cpu->readFloatRegBits(reg_idx, thread->readTid()); @@ -187,25 +175,12 @@ InOrderThreadContext::setIntReg(int reg_idx, uint64_t val) } void -InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val, int width) -{ - cpu->setFloatReg(reg_idx, val, thread->readTid(), width); -} - -void InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val) { cpu->setFloatReg(reg_idx, val, thread->readTid()); } void -InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val, - int width) -{ - cpu->setFloatRegBits(reg_idx, val, thread->readTid(), width); -} - -void InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val) { cpu->setFloatRegBits(reg_idx, val, thread->readTid()); diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index f3cf3ec44..327f8ac71 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -152,12 +152,8 @@ class InOrderThreadContext : public ThreadContext /** Reads an integer register. */ virtual uint64_t readIntReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx, int width); - virtual FloatReg readFloatReg(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx, int width); - virtual FloatRegBits readFloatRegBits(int reg_idx); virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid); @@ -165,12 +161,8 @@ class InOrderThreadContext : public ThreadContext /** Sets an integer register to a value. */ virtual void setIntReg(int reg_idx, uint64_t val); - virtual void setFloatReg(int reg_idx, FloatReg val, int width); - virtual void setFloatReg(int reg_idx, FloatReg val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val); virtual void setRegOtherThread(int misc_reg, const MiscReg &val, @@ -211,6 +203,12 @@ class InOrderThreadContext : public ThreadContext * write might have as defined by the architecture. */ virtual void setMiscReg(int misc_reg, const MiscReg &val); + virtual int flattenIntIndex(int reg) + { return cpu->isa[thread->readTid()].flattenIntIndex(reg); } + + virtual int flattenFloatIndex(int reg) + { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); } + virtual void activateContext(int delay) { cpu->activateContext(thread->readTid(), delay); } diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh index 803659487..9b3b39fcb 100644 --- a/src/cpu/inorder/thread_state.hh +++ b/src/cpu/inorder/thread_state.hh @@ -68,9 +68,9 @@ class InOrderThreadState : public ThreadState { InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num, - Process *_process, int _asid) + Process *_process) : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), 0/*_thread_num*/, - _process, 0/*_asid*/), + _process), cpu(_cpu), inSyscall(0), trapPending(0) { } diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc index 0ca02eeec..5face4391 100644 --- a/src/cpu/legiontrace.cc +++ b/src/cpu/legiontrace.cc @@ -46,7 +46,7 @@ #include <sys/shm.h> #include "arch/sparc/predecoder.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/utility.hh" #include "base/socket.hh" #include "cpu/base.hh" @@ -232,8 +232,7 @@ Trace::LegionTraceRecord::dump() } } for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { - if (thread->readFloatRegBits(i*2, - FloatRegFile::DoubleWidth) != + if (thread->readFloatRegBits(i*2) != shared_data->fpregs[i]) { diffFpRegs = true; } @@ -539,8 +538,7 @@ Trace::LegionTraceRecord::dump() char label[8]; sprintf(label, "%%f%d", x); printRegPair(outs, label, - thread->readFloatRegBits(x*2, - FloatRegFile::DoubleWidth), + thread->readFloatRegBits(x*2), shared_data->fpregs[x]); } } diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc index c23a9e4ad..fca8674f9 100644 --- a/src/cpu/nativetrace.cc +++ b/src/cpu/nativetrace.cc @@ -33,7 +33,7 @@ #include <errno.h> -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "arch/utility.hh" #include "base/loader/symtab.hh" #include "base/socket.hh" diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 621b6c1b9..6722941e4 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -361,7 +361,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) tid, this->thread[tid]); this->thread[tid] = new typename FullO3CPU<Impl>::Thread( (typename Impl::O3CPU *)(this), - tid, params->workload[tid], tid); + tid, params->workload[tid]); //usedTids[tid] = true; //threadMap[tid] = tid; @@ -372,7 +372,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) this->thread[tid] = new typename FullO3CPU<Impl>::Thread( (typename Impl::O3CPU *)(this), - tid, dummy_proc, tid); + tid, dummy_proc); //usedTids[tid] = false; } #endif // !FULL_SYSTEM @@ -1180,14 +1180,14 @@ template <class Impl> TheISA::MiscReg FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - return this->regFile.readMiscRegNoEffect(misc_reg, tid); + return this->isa[tid].readMiscRegNoEffect(misc_reg); } template <class Impl> TheISA::MiscReg FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) { - return this->regFile.readMiscReg(misc_reg, tid); + return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); } template <class Impl> @@ -1195,7 +1195,7 @@ void FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->regFile.setMiscRegNoEffect(misc_reg, val, tid); + this->isa[tid].setMiscRegNoEffect(misc_reg, val); } template <class Impl> @@ -1203,7 +1203,7 @@ void FullO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->regFile.setMiscReg(misc_reg, val, tid); + this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); } template <class Impl> @@ -1215,13 +1215,6 @@ FullO3CPU<Impl>::readIntReg(int reg_idx) template <class Impl> FloatReg -FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) -{ - return regFile.readFloatReg(reg_idx, width); -} - -template <class Impl> -FloatReg FullO3CPU<Impl>::readFloatReg(int reg_idx) { return regFile.readFloatReg(reg_idx); @@ -1229,13 +1222,6 @@ FullO3CPU<Impl>::readFloatReg(int reg_idx) template <class Impl> FloatRegBits -FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) -{ - return regFile.readFloatRegBits(reg_idx, width); -} - -template <class Impl> -FloatRegBits FullO3CPU<Impl>::readFloatRegBits(int reg_idx) { return regFile.readFloatRegBits(reg_idx); @@ -1250,13 +1236,6 @@ FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) template <class Impl> void -FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) -{ - regFile.setFloatReg(reg_idx, val, width); -} - -template <class Impl> -void FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) { regFile.setFloatReg(reg_idx, val); @@ -1264,13 +1243,6 @@ FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) template <class Impl> void -FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) -{ - regFile.setFloatRegBits(reg_idx, val, width); -} - -template <class Impl> -void FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) { regFile.setFloatRegBits(reg_idx, val); @@ -1287,7 +1259,7 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) template <class Impl> float -FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid) +FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) { int idx = reg_idx + TheISA::NumIntRegs; PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); @@ -1296,16 +1268,6 @@ FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid) } template <class Impl> -double -FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, ThreadID tid) -{ - int idx = reg_idx + TheISA::NumIntRegs; - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); - - return regFile.readFloatReg(phys_reg, 64); -} - -template <class Impl> uint64_t FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) { @@ -1326,7 +1288,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid) +FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) { int idx = reg_idx + TheISA::NumIntRegs; PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); @@ -1336,16 +1298,6 @@ FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, ThreadID tid) -{ - int idx = reg_idx + TheISA::NumIntRegs; - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); - - regFile.setFloatReg(phys_reg, val, 64); -} - -template <class Impl> -void FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) { int idx = reg_idx + TheISA::NumIntRegs; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 5cf27df75..0cc8eab78 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -392,23 +392,6 @@ class FullO3CPU : public BaseO3CPU /** Check if this address is a valid data address. */ bool validDataAddr(Addr addr) { return true; } - - /** Get instruction asid. */ - int getInstAsid(ThreadID tid) - { return regFile.miscRegs[tid].getInstAsid(); } - - /** Get data asid. */ - int getDataAsid(ThreadID tid) - { return regFile.miscRegs[tid].getDataAsid(); } -#else - /** Get instruction asid. */ - int getInstAsid(ThreadID tid) - { return thread[tid]->getInstAsid(); } - - /** Get data asid. */ - int getDataAsid(ThreadID tid) - { return thread[tid]->getDataAsid(); } - #endif /** Register accessors. Index refers to the physical register index. */ @@ -435,27 +418,17 @@ class FullO3CPU : public BaseO3CPU TheISA::FloatReg readFloatReg(int reg_idx); - TheISA::FloatReg readFloatReg(int reg_idx, int width); - TheISA::FloatRegBits readFloatRegBits(int reg_idx); - TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); - void setIntReg(int reg_idx, uint64_t val); void setFloatReg(int reg_idx, TheISA::FloatReg val); - void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); - void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); - void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); - uint64_t readArchIntReg(int reg_idx, ThreadID tid); - float readArchFloatRegSingle(int reg_idx, ThreadID tid); - - double readArchFloatRegDouble(int reg_idx, ThreadID tid); + float readArchFloatReg(int reg_idx, ThreadID tid); uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); @@ -466,9 +439,7 @@ class FullO3CPU : public BaseO3CPU */ void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); - void setArchFloatRegSingle(int reg_idx, float val, ThreadID tid); - - void setArchFloatRegDouble(int reg_idx, double val, ThreadID tid); + void setArchFloatReg(int reg_idx, float val, ThreadID tid); void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); @@ -603,6 +574,8 @@ class FullO3CPU : public BaseO3CPU /** Integer Register Scoreboard */ Scoreboard scoreboard; + TheISA::ISA isa[Impl::MaxThreads]; + public: /** Enum to give each stage a specific index, so when calling * activateStage() or deactivateStage(), they can specify which stage diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 292547b6b..3ef42e91f 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -196,22 +196,11 @@ class BaseO3DynInst : public BaseDynInst<Impl> return this->cpu->readIntReg(this->_srcRegIdx[idx]); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx], width); - } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return this->cpu->readFloatReg(this->_srcRegIdx[idx]); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) - { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width); - } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); @@ -226,13 +215,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> BaseDynInst<Impl>::setIntRegOperand(si, idx, val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width); - } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { this->cpu->setFloatReg(this->_destRegIdx[idx], val); @@ -240,13 +222,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh index 79e10524b..e28c4910e 100644 --- a/src/cpu/o3/free_list.hh +++ b/src/cpu/o3/free_list.hh @@ -34,7 +34,7 @@ #include <iostream> #include <queue> -#include "arch/isa_traits.hh" +#include "arch/registers.hh" #include "base/misc.hh" #include "base/trace.hh" #include "base/traceflags.hh" diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 07f8d487b..d6beecdc5 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -33,7 +33,6 @@ #define __CPU_O3_REGFILE_HH__ #include "arch/isa_traits.hh" -#include "arch/regfile.hh" #include "arch/types.hh" #include "base/trace.hh" #include "config/full_system.hh" @@ -57,8 +56,6 @@ class PhysRegFile typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::MiscRegFile MiscRegFile; - typedef TheISA::MiscReg MiscReg; typedef union { FloatReg d; @@ -95,21 +92,6 @@ class PhysRegFile return intRegFile[reg_idx]; } - FloatReg readFloatReg(PhysRegIndex reg_idx, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); - - FloatReg floatReg = floatRegFile[reg_idx].d; - - DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " - "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); - - return floatReg; - } - /** Reads a floating point register (double precision). */ FloatReg readFloatReg(PhysRegIndex reg_idx) { @@ -126,22 +108,6 @@ class PhysRegFile return floatReg; } - /** Reads a floating point register as an integer. */ - FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); - - FloatRegBits floatRegBits = floatRegFile[reg_idx].q; - - DPRINTF(IEW, "RegFile: Access to float register %i as int, " - "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); - - return floatRegBits; - } - FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) { // Remove the base Float reg dependency. @@ -169,23 +135,6 @@ class PhysRegFile intRegFile[reg_idx] = val; } - /** Sets a single precision floating point register to the given value. */ - void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs); - - DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", - int(reg_idx), (uint64_t)val); - -#if THE_ISA == ALPHA_ISA - if (reg_idx != TheISA::ZeroReg) -#endif - floatRegFile[reg_idx].d = val; - } - /** Sets a double precision floating point register to the given value. */ void setFloatReg(PhysRegIndex reg_idx, FloatReg val) { @@ -203,20 +152,6 @@ class PhysRegFile floatRegFile[reg_idx].d = val; } - /** Sets a floating point register to the given integer value. */ - void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs); - - DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", - int(reg_idx), (uint64_t)val); - - floatRegFile[reg_idx].q = val; - } - void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) { // Remove the base Float reg dependency. @@ -230,30 +165,6 @@ class PhysRegFile floatRegFile[reg_idx].q = val; } - MiscReg - readMiscRegNoEffect(int misc_reg, ThreadID tid) - { - return miscRegs[tid].readRegNoEffect(misc_reg); - } - - MiscReg - readMiscReg(int misc_reg, ThreadID tid) - { - return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid)); - } - - void - setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) - { - miscRegs[tid].setRegNoEffect(misc_reg, val); - } - - void - setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid) - { - miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid)); - } - public: /** (signed) integer register file. */ IntReg *intRegFile; @@ -261,9 +172,6 @@ class PhysRegFile /** Floating point register file. */ PhysFloatReg *floatRegFile; - /** Miscellaneous register file. */ - MiscRegFile miscRegs[Impl::MaxThreads]; - #if FULL_SYSTEM private: int intrflag; // interrupt flag @@ -289,10 +197,6 @@ PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, intRegFile = new IntReg[numPhysicalIntRegs]; floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; - for (int i = 0; i < Impl::MaxThreads; ++i) { - miscRegs[i].clear(); - } - memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); } diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 2bca6f81c..e4cc2674b 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -32,7 +32,7 @@ #include <list> #include "arch/isa_traits.hh" -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "config/full_system.hh" #include "cpu/o3/rename.hh" #include "params/DerivO3CPU.hh" @@ -959,11 +959,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) RegIndex src_reg = inst->srcRegIdx(src_idx); RegIndex flat_src_reg = src_reg; if (src_reg < TheISA::FP_Base_DepTag) { - flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); + flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); } else if (src_reg < TheISA::Ctrl_Base_DepTag) { src_reg = src_reg - TheISA::FP_Base_DepTag; - flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg); + flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); flat_src_reg += TheISA::NumIntRegs; } else { flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; @@ -1009,7 +1009,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) RegIndex flat_dest_reg = dest_reg; if (dest_reg < TheISA::FP_Base_DepTag) { // Integer registers are flattened. - flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); + flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); } else { // Floating point and Miscellaneous registers need their indexes diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index b10305d5d..ed5c6ac20 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -167,23 +167,15 @@ class O3ThreadContext : public ThreadContext /** Reads an integer register. */ virtual uint64_t readIntReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx, int width); - virtual FloatReg readFloatReg(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx, int width); - virtual FloatRegBits readFloatRegBits(int reg_idx); /** Sets an integer register to a value. */ virtual void setIntReg(int reg_idx, uint64_t val); - virtual void setFloatReg(int reg_idx, FloatReg val, int width); - virtual void setFloatReg(int reg_idx, FloatReg val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val); /** Reads this thread's PC. */ @@ -226,6 +218,9 @@ class O3ThreadContext : public ThreadContext * write might have as defined by the architecture. */ virtual void setMiscReg(int misc_reg, const MiscReg &val); + virtual int flattenIntIndex(int reg); + virtual int flattenFloatIndex(int reg); + /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. virtual unsigned readStCondFailures() diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index bce334dc4..e631c9244 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -29,7 +29,7 @@ * Korey Sewell */ -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "cpu/o3/thread_context.hh" #include "cpu/quiesce_event.hh" @@ -272,48 +272,23 @@ template <class Impl> uint64_t O3ThreadContext<Impl>::readIntReg(int reg_idx) { - reg_idx = TheISA::flattenIntIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); return cpu->readArchIntReg(reg_idx, thread->threadId()); } template <class Impl> TheISA::FloatReg -O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) -{ - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - switch(width) { - case 32: - return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); - case 64: - return cpu->readArchFloatRegDouble(reg_idx, thread->threadId()); - default: - panic("Unsupported width!"); - return 0; - } -} - -template <class Impl> -TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); -} - -template <class Impl> -TheISA::FloatRegBits -O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) -{ - DPRINTF(Fault, "Reading floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); + return cpu->readArchFloatReg(reg_idx, thread->threadId()); } template <class Impl> TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); } @@ -321,7 +296,7 @@ template <class Impl> void O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) { - reg_idx = TheISA::flattenIntIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); cpu->setArchIntReg(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -332,30 +307,10 @@ O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) template <class Impl> void -O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) -{ - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - switch(width) { - case 32: - cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); - break; - case 64: - cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId()); - break; - } - - // Squash if we're not already in a state update mode. - if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->threadId()); - } -} - -template <class Impl> -void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); + cpu->setArchFloatReg(reg_idx, val, thread->threadId()); if (!thread->trapPending && !thread->inSyscall) { cpu->squashFromTC(thread->threadId()); @@ -364,24 +319,9 @@ O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) template <class Impl> void -O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, - int width) -{ - DPRINTF(Fault, "Setting floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); - - // Squash if we're not already in a state update mode. - if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->threadId()); - } -} - -template <class Impl> -void O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -439,6 +379,20 @@ O3ThreadContext<Impl>::setNextMicroPC(uint64_t val) } template <class Impl> +int +O3ThreadContext<Impl>::flattenIntIndex(int reg) +{ + return cpu->isa[thread->threadId()].flattenIntIndex(reg); +} + +template <class Impl> +int +O3ThreadContext<Impl>::flattenFloatIndex(int reg) +{ + return cpu->isa[thread->threadId()].flattenFloatIndex(reg); +} + +template <class Impl> void O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 1f0e7a3bb..1171053b9 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -95,8 +95,8 @@ struct O3ThreadState : public ThreadState { profilePC = 3; } #else - O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid) - : ThreadState(_cpu, _thread_num, _process, _asid), + O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process) + : ThreadState(_cpu, _thread_num, _process), cpu(_cpu), inSyscall(0), trapPending(0) { } #endif diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 2e21411ae..5e36332af 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -33,7 +33,6 @@ #include <set> -#include "arch/regfile.hh" #include "base/statistics.hh" #include "base/timebuf.hh" #include "config/full_system.hh" @@ -183,22 +182,14 @@ class OzoneCPU : public BaseCPU uint64_t readIntReg(int reg_idx); - FloatReg readFloatReg(int reg_idx, int width); - FloatReg readFloatReg(int reg_idx); - FloatRegBits readFloatRegBits(int reg_idx, int width); - FloatRegBits readFloatRegBits(int reg_idx); void setIntReg(int reg_idx, uint64_t val); - void setFloatReg(int reg_idx, FloatReg val, int width); - void setFloatReg(int reg_idx, FloatReg val); - void setFloatRegBits(int reg_idx, FloatRegBits val, int width); - void setFloatRegBits(int reg_idx, FloatRegBits val); uint64_t readPC() { return thread->PC; } diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 25fa64071..f86b882d1 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -918,22 +918,6 @@ OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx) } template <class Impl> -TheISA::FloatReg -OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width) -{ - int idx = reg_idx + TheISA::FP_Base_DepTag; - switch(width) { - case 32: - return thread->renameTable[idx]->readFloatResult(); - case 64: - return thread->renameTable[idx]->readDoubleResult(); - default: - panic("Unsupported width!"); - return 0; - } -} - -template <class Impl> double OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx) { @@ -943,14 +927,6 @@ OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx) template <class Impl> uint64_t -OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width) -{ - int idx = reg_idx + TheISA::FP_Base_DepTag; - return thread->renameTable[idx]->readIntResult(); -} - -template <class Impl> -uint64_t OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx) { int idx = reg_idx + TheISA::FP_Base_DepTag; @@ -970,27 +946,6 @@ OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val) template <class Impl> void -OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width) -{ - int idx = reg_idx + TheISA::FP_Base_DepTag; - switch(width) { - case 32: - panic("Unimplemented!"); - break; - case 64: - thread->renameTable[idx]->setDoubleResult(val); - break; - default: - panic("Unsupported width!"); - } - - if (!thread->inSyscall) { - cpu->squashFromTC(); - } -} - -template <class Impl> -void OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val) { int idx = reg_idx + TheISA::FP_Base_DepTag; @@ -1004,14 +959,6 @@ OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val) template <class Impl> void -OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val, - int width) -{ - panic("Unimplemented!"); -} - -template <class Impl> -void OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val) { panic("Unimplemented!"); diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index e138cbe13..a39f383ba 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -151,28 +151,14 @@ class OzoneDynInst : public BaseDynInst<Impl> return srcInsts[idx]->readIntResult(); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - switch(width) { - case 32: - return srcInsts[idx]->readFloatResult(); - case 64: - return srcInsts[idx]->readDoubleResult(); - default: - panic("Width not supported"); - return 0; - } - } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return srcInsts[idx]->readFloatResult(); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { - return srcInsts[idx]->readIntResult(); + return srcInsts[idx]->readFloatResult(); } FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) @@ -188,24 +174,12 @@ class OzoneDynInst : public BaseDynInst<Impl> BaseDynInst<Impl>::setIntReg(si, idx, val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - BaseDynInst<Impl>::setFloatReg(si, idx, val, width); - } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { BaseDynInst<Impl>::setFloatReg(si, idx, val); } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - BaseDynInst<Impl>::setFloatRegBits(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { BaseDynInst<Impl>::setFloatRegBits(si, idx, val); diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index 53776e7d9..971fba886 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -86,9 +86,8 @@ struct OzoneThreadState : public ThreadState { miscRegFile.clear(); } #else - OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process, - int _asid) - : ThreadState(_cpu, -1, _thread_num, _process, _asid), + OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process) + : ThreadState(_cpu, -1, _thread_num, _process), cpu(_cpu), inSyscall(0), trapPending(0) { miscRegFile.clear(); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 279fb98b7..921c8c19d 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -78,7 +78,7 @@ BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); #else thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], - p->itb, p->dtb, /* asid */ 0); + p->itb, p->dtb); #endif // !FULL_SYSTEM thread->setStatus(ThreadContext::Halted); diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 4e71d677e..466d0d1c9 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -262,25 +262,12 @@ class BaseSimpleCPU : public BaseCPU return thread->readIntReg(si->srcRegIdx(idx)); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return thread->readFloatReg(reg_idx, width); - } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatReg(reg_idx); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return thread->readFloatRegBits(reg_idx, width); - } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; @@ -292,13 +279,6 @@ class BaseSimpleCPU : public BaseCPU thread->setIntReg(si->destRegIdx(idx), val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - thread->setFloatReg(reg_idx, val, width); - } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; @@ -306,13 +286,6 @@ class BaseSimpleCPU : public BaseCPU } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - thread->setFloatRegBits(reg_idx, val, width); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 73b23f89a..22bc283a3 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -63,15 +63,15 @@ using namespace std; SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, TheISA::TLB *_itb, TheISA::TLB *_dtb, bool use_kernel_stats) - : ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb), - dtb(_dtb) + : ThreadState(_cpu, _thread_num), + cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) { tc = new ProxyThreadContext<SimpleThread>(this); quiesceEvent = new EndQuiesceEvent(tc); - regs.clear(); + clearArchRegs(); if (cpu->params()->profile) { profile = new FunctionProfile(system->kernelSymtab); @@ -92,11 +92,11 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, } #else SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, - TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid) - : ThreadState(_cpu, _thread_num, _process, _asid), + TheISA::TLB *_itb, TheISA::TLB *_dtb) + : ThreadState(_cpu, _thread_num, _process), cpu(_cpu), itb(_itb), dtb(_dtb) { - regs.clear(); + clearArchRegs(); tc = new ProxyThreadContext<SimpleThread>(this); } @@ -106,11 +106,10 @@ SimpleThread::SimpleThread() #if FULL_SYSTEM : ThreadState(NULL, -1) #else - : ThreadState(NULL, -1, NULL, -1) + : ThreadState(NULL, -1, NULL) #endif { tc = new ProxyThreadContext<SimpleThread>(this); - regs.clear(); } SimpleThread::~SimpleThread() @@ -191,7 +190,13 @@ void SimpleThread::serialize(ostream &os) { ThreadState::serialize(os); - regs.serialize(cpu, os); + SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); + SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); + SERIALIZE_SCALAR(microPC); + SERIALIZE_SCALAR(nextMicroPC); + SERIALIZE_SCALAR(PC); + SERIALIZE_SCALAR(nextPC); + SERIALIZE_SCALAR(nextNPC); // thread_num and cpu_id are deterministic from the config } @@ -200,7 +205,13 @@ void SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) { ThreadState::unserialize(cp, section); - regs.unserialize(cpu, cp, section); + UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); + UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); + UNSERIALIZE_SCALAR(microPC); + UNSERIALIZE_SCALAR(nextMicroPC); + UNSERIALIZE_SCALAR(PC); + UNSERIALIZE_SCALAR(nextPC); + UNSERIALIZE_SCALAR(nextNPC); // thread_num and cpu_id are deterministic from the config } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 08dd45640..d9d624e77 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -32,9 +32,11 @@ #ifndef __CPU_SIMPLE_THREAD_HH__ #define __CPU_SIMPLE_THREAD_HH__ +#include "arch/isa.hh" #include "arch/isa_traits.hh" -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "arch/tlb.hh" +#include "arch/types.hh" #include "base/types.hh" #include "config/full_system.hh" #include "cpu/thread_context.hh" @@ -88,9 +90,7 @@ class TranslatingPort; class SimpleThread : public ThreadState { protected: - typedef TheISA::RegFile RegFile; typedef TheISA::MachInst MachInst; - typedef TheISA::MiscRegFile MiscRegFile; typedef TheISA::MiscReg MiscReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; @@ -98,7 +98,34 @@ class SimpleThread : public ThreadState typedef ThreadContext::Status Status; protected: - RegFile regs; // correct-path register context + union { + FloatReg f[TheISA::NumFloatRegs]; + FloatRegBits i[TheISA::NumFloatRegs]; + } floatRegs; + TheISA::IntReg intRegs[TheISA::NumIntRegs]; + TheISA::ISA isa; // one "instance" of the current ISA. + + /** The current microcode pc for the currently executing macro + * operation. + */ + MicroPC microPC; + + /** The next microcode pc for the currently executing macro + * operation. + */ + MicroPC nextMicroPC; + + /** The current pc. + */ + Addr PC; + + /** The next pc. + */ + Addr nextPC; + + /** The next next pc. + */ + Addr nextNPC; public: // pointer to CPU associated with this SimpleThread @@ -118,7 +145,7 @@ class SimpleThread : public ThreadState bool use_kernel_stats = true); #else SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, - TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid); + TheISA::TLB *_itb, TheISA::TLB *_dtb); #endif SimpleThread(); @@ -164,9 +191,6 @@ class SimpleThread : public ThreadState } #if FULL_SYSTEM - int getInstAsid() { return regs.instAsid(); } - int getDataAsid() { return regs.dataAsid(); } - void dumpFuncProfile(); Fault hwrei(); @@ -222,79 +246,68 @@ class SimpleThread : public ThreadState void copyArchRegs(ThreadContext *tc); - void clearArchRegs() { regs.clear(); } + void clearArchRegs() + { + microPC = 0; + nextMicroPC = 1; + PC = nextPC = nextNPC = 0; + memset(intRegs, 0, sizeof(intRegs)); + memset(floatRegs.i, 0, sizeof(floatRegs.i)); + } // // New accessors for new decoder. // uint64_t readIntReg(int reg_idx) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); - return regs.readIntReg(flatIndex); - } - - FloatReg readFloatReg(int reg_idx, int width) - { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - return regs.readFloatReg(flatIndex, width); + int flatIndex = isa.flattenIntIndex(reg_idx); + assert(flatIndex < TheISA::NumIntRegs); + return intRegs[flatIndex]; } FloatReg readFloatReg(int reg_idx) { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - return regs.readFloatReg(flatIndex); - } - - FloatRegBits readFloatRegBits(int reg_idx, int width) - { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - return regs.readFloatRegBits(flatIndex, width); + int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); + return floatRegs.f[flatIndex]; } FloatRegBits readFloatRegBits(int reg_idx) { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - return regs.readFloatRegBits(flatIndex); + int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); + return floatRegs.i[flatIndex]; } void setIntReg(int reg_idx, uint64_t val) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); - regs.setIntReg(flatIndex, val); - } - - void setFloatReg(int reg_idx, FloatReg val, int width) - { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - regs.setFloatReg(flatIndex, val, width); + int flatIndex = isa.flattenIntIndex(reg_idx); + assert(flatIndex < TheISA::NumIntRegs); + intRegs[flatIndex] = val; } void setFloatReg(int reg_idx, FloatReg val) { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - regs.setFloatReg(flatIndex, val); - } - - void setFloatRegBits(int reg_idx, FloatRegBits val, int width) - { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - regs.setFloatRegBits(flatIndex, val, width); + int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); + floatRegs.f[flatIndex] = val; } void setFloatRegBits(int reg_idx, FloatRegBits val) { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - regs.setFloatRegBits(flatIndex, val); + int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); + floatRegs.i[flatIndex] = val; } uint64_t readPC() { - return regs.readPC(); + return PC; } void setPC(uint64_t val) { - regs.setPC(val); + PC = val; } uint64_t readMicroPC() @@ -309,12 +322,12 @@ class SimpleThread : public ThreadState uint64_t readNextPC() { - return regs.readNextPC(); + return nextPC; } void setNextPC(uint64_t val) { - regs.setNextPC(val); + nextPC = val; } uint64_t readNextMicroPC() @@ -329,36 +342,54 @@ class SimpleThread : public ThreadState uint64_t readNextNPC() { - return regs.readNextNPC(); +#if ISA_HAS_DELAY_SLOT + return nextNPC; +#else + return nextPC + sizeof(TheISA::MachInst); +#endif } void setNextNPC(uint64_t val) { - regs.setNextNPC(val); +#if ISA_HAS_DELAY_SLOT + nextNPC = val; +#endif } MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) { - return regs.readMiscRegNoEffect(misc_reg); + return isa.readMiscRegNoEffect(misc_reg); } MiscReg readMiscReg(int misc_reg, ThreadID tid = 0) { - return regs.readMiscReg(misc_reg, tc); + return isa.readMiscReg(misc_reg, tc); } void setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) { - return regs.setMiscRegNoEffect(misc_reg, val); + return isa.setMiscRegNoEffect(misc_reg, val); } void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) { - return regs.setMiscReg(misc_reg, val, tc); + return isa.setMiscReg(misc_reg, val, tc); + } + + int + flattenIntIndex(int reg) + { + return isa.flattenIntIndex(reg); + } + + int + flattenFloatIndex(int reg) + { + return isa.flattenFloatIndex(reg); } unsigned readStCondFailures() { return storeCondFailures; } diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 3e37572d8..9e34204ef 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -31,7 +31,7 @@ #ifndef __CPU_THREAD_CONTEXT_HH__ #define __CPU_THREAD_CONTEXT_HH__ -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "arch/types.hh" #include "base/types.hh" #include "config/full_system.hh" @@ -79,12 +79,10 @@ namespace TheISA { class ThreadContext { protected: - typedef TheISA::RegFile RegFile; typedef TheISA::MachInst MachInst; typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::MiscRegFile MiscRegFile; typedef TheISA::MiscReg MiscReg; public: @@ -188,24 +186,16 @@ class ThreadContext // virtual uint64_t readIntReg(int reg_idx) = 0; - virtual FloatReg readFloatReg(int reg_idx, int width) = 0; - virtual FloatReg readFloatReg(int reg_idx) = 0; - virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; - virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; virtual void setIntReg(int reg_idx, uint64_t val) = 0; - virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; - virtual void setFloatReg(int reg_idx, FloatReg val) = 0; virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; - virtual uint64_t readPC() = 0; virtual void setPC(uint64_t val) = 0; @@ -234,6 +224,9 @@ class ThreadContext virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; + virtual int flattenIntIndex(int reg) = 0; + virtual int flattenFloatIndex(int reg) = 0; + virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid) { @@ -375,30 +368,18 @@ class ProxyThreadContext : public ThreadContext uint64_t readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } - FloatReg readFloatReg(int reg_idx, int width) - { return actualTC->readFloatReg(reg_idx, width); } - FloatReg readFloatReg(int reg_idx) { return actualTC->readFloatReg(reg_idx); } - FloatRegBits readFloatRegBits(int reg_idx, int width) - { return actualTC->readFloatRegBits(reg_idx, width); } - FloatRegBits readFloatRegBits(int reg_idx) { return actualTC->readFloatRegBits(reg_idx); } void setIntReg(int reg_idx, uint64_t val) { actualTC->setIntReg(reg_idx, val); } - void setFloatReg(int reg_idx, FloatReg val, int width) - { actualTC->setFloatReg(reg_idx, val, width); } - void setFloatReg(int reg_idx, FloatReg val) { actualTC->setFloatReg(reg_idx, val); } - void setFloatRegBits(int reg_idx, FloatRegBits val, int width) - { actualTC->setFloatRegBits(reg_idx, val, width); } - void setFloatRegBits(int reg_idx, FloatRegBits val) { actualTC->setFloatRegBits(reg_idx, val); } @@ -434,6 +415,12 @@ class ProxyThreadContext : public ThreadContext void setMiscReg(int misc_reg, const MiscReg &val) { return actualTC->setMiscReg(misc_reg, val); } + int flattenIntIndex(int reg) + { return actualTC->flattenIntIndex(reg); } + + int flattenFloatIndex(int reg) + { return actualTC->flattenFloatIndex(reg); } + unsigned readStCondFailures() { return actualTC->readStCondFailures(); } diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index d9d83fb00..c62a7a3be 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -45,8 +45,7 @@ #if FULL_SYSTEM ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid) #else -ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, - Process *_process, short _asid) +ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) #endif : numInst(0), numLoad(0), _status(ThreadContext::Halted), baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0), @@ -54,9 +53,9 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), kernelStats(NULL), physPort(NULL), virtPort(NULL), #else - port(NULL), process(_process), asid(_asid), + port(NULL), process(_process), #endif - microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) + funcExeInst(0), storeCondFailures(0) { } @@ -77,8 +76,6 @@ ThreadState::serialize(std::ostream &os) // thread_num and cpu_id are deterministic from the config SERIALIZE_SCALAR(funcExeInst); SERIALIZE_SCALAR(inst); - SERIALIZE_SCALAR(microPC); - SERIALIZE_SCALAR(nextMicroPC); #if FULL_SYSTEM Tick quiesceEndTick = 0; @@ -98,8 +95,6 @@ ThreadState::unserialize(Checkpoint *cp, const std::string §ion) // thread_num and cpu_id are deterministic from the config UNSERIALIZE_SCALAR(funcExeInst); UNSERIALIZE_SCALAR(inst); - UNSERIALIZE_SCALAR(microPC); - UNSERIALIZE_SCALAR(nextMicroPC); #if FULL_SYSTEM Tick quiesceEndTick; diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 525ecca86..5c7c0ea56 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -68,7 +68,7 @@ struct ThreadState { #if FULL_SYSTEM ThreadState(BaseCPU *cpu, ThreadID _tid); #else - ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process, short _asid); + ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process); #endif ~ThreadState(); @@ -119,9 +119,6 @@ struct ThreadState { TranslatingPort *getMemPort(); void setMemPort(TranslatingPort *_port) { port = _port; } - - int getInstAsid() { return asid; } - int getDataAsid() { return asid; } #endif /** Sets the current instruction being committed. */ @@ -205,12 +202,6 @@ struct ThreadState { TranslatingPort *port; Process *process; - - // Address space ID. Note that this is used for TIMING cache - // simulation only; all functional memory accesses should use - // one of the FunctionalMemory pointers above. - short asid; - #endif /** Current instruction the thread is committing. Only set and @@ -218,16 +209,6 @@ struct ThreadState { */ TheISA::MachInst inst; - /** The current microcode pc for the currently executing macro - * operation. - */ - MicroPC microPC; - - /** The next microcode pc for the currently executing macro - * operation. - */ - MicroPC nextMicroPC; - public: /** * Temporary storage to pass the source address from copy_load to diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh index 2234f55fe..bf46e0de4 100644 --- a/src/kern/tru64/tru64.hh +++ b/src/kern/tru64/tru64.hh @@ -55,6 +55,7 @@ class Tru64 {}; #include <string.h> // for memset() #include <unistd.h> +#include "arch/alpha/registers.hh" #include "cpu/base.hh" #include "sim/core.hh" #include "sim/syscall_emul.hh" @@ -495,7 +496,6 @@ class Tru64 : public OperatingSystem { using namespace TheISA; - using TheISA::RegFile; TypedBufferArg<Tru64::sigcontext> sc(process->getSyscallArg(tc, 0)); sc.copyIn(tc->getMemPort()); diff --git a/src/mem/physical.cc b/src/mem/physical.cc index e6150c548..5680fd970 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -39,7 +39,7 @@ #include <iostream> #include <string> -#include "arch/isa_traits.hh" +#include "arch/registers.hh" #include "base/misc.hh" #include "base/random.hh" #include "base/types.hh" diff --git a/src/sim/process.hh b/src/sim/process.hh index db52e1697..0d5421dcd 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -44,7 +44,7 @@ #include <string> #include <vector> -#include "arch/types.hh" +#include "arch/registers.hh" #include "base/statistics.hh" #include "base/types.hh" #include "sim/sim_object.hh" diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc index 941c56530..811bdb73a 100644 --- a/src/sim/syscall_emul.cc +++ b/src/sim/syscall_emul.cc @@ -692,7 +692,7 @@ cloneFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ctc->setIntReg(NumIntArchRegs + 4, 0); ctc->setIntReg(NumIntArchRegs + 3, NWindows - 2); ctc->setIntReg(NumIntArchRegs + 5, NWindows); - ctc->setMiscRegNoEffect(MISCREG_CWP, 0); + ctc->setMiscReg(MISCREG_CWP, 0); ctc->setIntReg(NumIntArchRegs + 7, 0); ctc->setMiscRegNoEffect(MISCREG_TL, 0); ctc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); |