X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm.

--HG--
extra : convert_revision : 02c6641200edb133c9bc11f1fdf3c1a0b1c87e77

2 files changed, 46 insertions, 0 deletions

diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc
index 0db61af2c..7152602fe 100644
--- a/src/cpu/nativetrace.cc
+++ b/src/cpu/nativetrace.cc
@@ -84,6 +84,19 @@ NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
     return true;
 }
 
+bool
+NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
+{
+    if (mXmmBuf[num * 2]     != nXmmBuf[num * 2] ||
+        mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
+        DPRINTFN("Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
+                num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
+                     mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
+        return false;
+    }
+    return true;
+}
+
 void
 Trace::NativeTraceRecord::dump()
 {
@@ -127,6 +140,22 @@ Trace::NativeTrace::check(ThreadContext * tc, bool isSyscall)
     checkReg("r14", mState.r14, nState.r14);
     checkReg("r15", mState.r15, nState.r15);
     checkReg("rip", mState.rip, nState.rip);
+    checkXMM(0, mState.xmm, nState.xmm);
+    checkXMM(1, mState.xmm, nState.xmm);
+    checkXMM(2, mState.xmm, nState.xmm);
+    checkXMM(3, mState.xmm, nState.xmm);
+    checkXMM(4, mState.xmm, nState.xmm);
+    checkXMM(5, mState.xmm, nState.xmm);
+    checkXMM(6, mState.xmm, nState.xmm);
+    checkXMM(7, mState.xmm, nState.xmm);
+    checkXMM(8, mState.xmm, nState.xmm);
+    checkXMM(9, mState.xmm, nState.xmm);
+    checkXMM(10, mState.xmm, nState.xmm);
+    checkXMM(11, mState.xmm, nState.xmm);
+    checkXMM(12, mState.xmm, nState.xmm);
+    checkXMM(13, mState.xmm, nState.xmm);
+    checkXMM(14, mState.xmm, nState.xmm);
+    checkXMM(15, mState.xmm, nState.xmm);
 #if THE_ISA == SPARC_ISA
     /*for(int f = 0; f <= 62; f+=2)
     {
diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh
index 6fd624211..ab038c4c3 100644
--- a/src/cpu/nativetrace.hh
+++ b/src/cpu/nativetrace.hh
@@ -37,6 +37,7 @@
 #include "sim/host.hh"
 #include "sim/insttracer.hh"
 #include "arch/x86/intregs.hh"
+#include "arch/x86/floatregs.hh"
 
 class ThreadContext;
 
@@ -91,6 +92,9 @@ class NativeTrace : public InstTracer
         uint64_t r14;
         uint64_t r15;
         uint64_t rip;
+        //This should be expanded to 16 if x87 registers are considered
+        uint64_t mmx[8];
+        uint64_t xmm[32];
 
         void update(int fd)
         {
@@ -121,6 +125,11 @@ class NativeTrace : public InstTracer
             r14 = TheISA::gtoh(r14);
             r15 = TheISA::gtoh(r15);
             rip = TheISA::gtoh(rip);
+            //This should be expanded if x87 registers are considered
+            for (int i = 0; i < 8; i++)
+                mmx[i] = TheISA::gtoh(mmx[i]);
+            for (int i = 0; i < 32; i++)
+                xmm[i] = TheISA::gtoh(xmm[i]);
         }
 
         void update(ThreadContext * tc)
@@ -142,6 +151,11 @@ class NativeTrace : public InstTracer
             r14 = tc->readIntReg(X86ISA::INTREG_R14);
             r15 = tc->readIntReg(X86ISA::INTREG_R15);
             rip = tc->readNextPC();
+            //This should be expanded if x87 registers are considered
+            for (int i = 0; i < 8; i++)
+                mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
+            for (int i = 0; i < 32; i++)
+                xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
         }
 
     };
@@ -171,6 +185,9 @@ class NativeTrace : public InstTracer
     bool
     checkR11Reg(const char * regName, uint64_t &, uint64_t &);
 
+    bool
+    checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[]);
+
     NativeTrace(const Params *p);
 
     NativeTraceRecord *