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authorNikos Nikoleris <nikos.nikoleris@arm.com>2018-11-06 11:24:01 +0000
committerNikos Nikoleris <nikos.nikoleris@arm.com>2018-11-13 14:13:26 +0000
commit2f52a9b65ee37ba8f34ac3d46f96dca9afc02c7c (patch)
tree0ff1b7b5146a5c0ec1935d43b7ce30405d1bdcde /src
parentd8705a73771ea213b1e52c6cdfad3bd05b3210c5 (diff)
downloadgem5-2f52a9b65ee37ba8f34ac3d46f96dca9afc02c7c.tar.xz
mem-cache: Align how we handle requests in atomic with timing
Requests, for which a cache has already committed to respond do not perform any lookups. Previously in atomic mode the packet would pay the lookup latency while in timing it wouldn't. This patch aligns recvAtomic with recvTimingReq and removes the lookup latency from the the handling of such requests. Change-Id: I50a0631f8058e5086d94d55af0e1788a60e2883f Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14175 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src')
-rw-r--r--src/mem/cache/base.cc23
-rw-r--r--src/mem/cache/cache.cc15
2 files changed, 19 insertions, 19 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 8f7a8922d..ec0383dea 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -569,29 +569,14 @@ BaseCache::recvTimingResp(PacketPtr pkt)
Tick
BaseCache::recvAtomic(PacketPtr pkt)
{
- // We are in atomic mode so we pay just for lookupLatency here.
- Cycles lat = lookupLatency;
-
- // follow the same flow as in recvTimingReq, and check if a cache
- // above us is responding
- if (pkt->cacheResponding() && !pkt->isClean()) {
- assert(!pkt->req->isCacheInvalidate());
- DPRINTF(Cache, "Cache above responding to %s: not responding\n",
- pkt->print());
-
- // if a cache is responding, and it had the line in Owned
- // rather than Modified state, we need to invalidate any
- // copies that are not on the same path to memory
- assert(pkt->needsWritable() && !pkt->responderHadWritable());
- lat += ticksToCycles(memSidePort.sendAtomic(pkt));
-
- return lat * clockPeriod();
- }
-
// should assert here that there are no outstanding MSHRs or
// writebacks... that would mean that someone used an atomic
// access in timing mode
+ // We use lookupLatency here because it is used to specify the latency
+ // to access.
+ Cycles lat = lookupLatency;
+
CacheBlk *blk = nullptr;
PacketList writebacks;
bool satisfied = access(pkt, blk, lat, writebacks);
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 3bb2667af..624f244ce 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -658,6 +658,21 @@ Cache::recvAtomic(PacketPtr pkt)
{
promoteWholeLineWrites(pkt);
+ // follow the same flow as in recvTimingReq, and check if a cache
+ // above us is responding
+ if (pkt->cacheResponding()) {
+ assert(!pkt->req->isCacheInvalidate());
+ DPRINTF(Cache, "Cache above responding to %s: not responding\n",
+ pkt->print());
+
+ // if a cache is responding, and it had the line in Owned
+ // rather than Modified state, we need to invalidate any
+ // copies that are not on the same path to memory
+ assert(pkt->needsWritable() && !pkt->responderHadWritable());
+
+ return memSidePort.sendAtomic(pkt);
+ }
+
return BaseCache::recvAtomic(pkt);
}