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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-12-23 09:31:18 -0500 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-12-23 09:31:18 -0500 |
commit | 4acd4a205525a79555f783767ab0d6a5f9c31eb5 (patch) | |
tree | ef27988850939642b3f40adcd6e8172bbc4d5508 /src | |
parent | df82a2d00311b96ec7fefc901232ba01bbf26d39 (diff) | |
download | gem5-4acd4a205525a79555f783767ab0d6a5f9c31eb5.tar.xz |
mem: Fix bug relating to writebacks and prefetches
Previously the code commented about an unhandled case where it might be
possible for a writeback to arrive after a prefetch was generated but
before it was sent to the memory system. I hit that case. Luckily
the prefetchSquash() logic already in the code handles dropping prefetch
request in certian circumstances.
Diffstat (limited to 'src')
-rw-r--r-- | src/mem/cache/cache_impl.hh | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 15e9bc0fb..115e7aeb8 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1892,12 +1892,6 @@ Cache<TagStore>::getTimingPacket() BlkType *blk = tags->findBlock(mshr->addr, mshr->isSecure); if (tgt_pkt->cmd == MemCmd::HardPFReq) { - // It might be possible for a writeback to arrive between - // the time the prefetch is placed in the MSHRs and when - // it's selected to send... if so, this assert will catch - // that, and then we'll have to figure out what to do. - assert(blk == NULL); - // We need to check the caches above us to verify that // they don't have a copy of this block in the dirty state // at the moment. Without this check we could get a stale @@ -1909,8 +1903,10 @@ Cache<TagStore>::getTimingPacket() cpuSidePort->sendTimingSnoopReq(&snoop_pkt); // Check to see if the prefetch was squashed by an upper cache - if (snoop_pkt.prefetchSquashed()) { - DPRINTF(Cache, "Prefetch squashed by upper cache. " + // Or if a writeback arrived between the time the prefetch was + // placed in the MSHRs and when it was selected to send. + if (snoop_pkt.prefetchSquashed() || blk != NULL) { + DPRINTF(Cache, "Prefetch squashed by cache. " "Deallocating mshr target %#x.\n", mshr->addr); // Deallocate the mshr target |