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authorGabe Black <gblack@eecs.umich.edu>2009-08-07 10:12:58 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-07 10:12:58 -0700
commit62a2e85c9a0af39970568b35afa4d050ef571b23 (patch)
tree48202cf01e67549878985fb2b8756b0217681381 /src
parent0526f453aa1286dd43b2196da367500650a0e424 (diff)
downloadgem5-62a2e85c9a0af39970568b35afa4d050ef571b23.tar.xz
X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend.
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
index ac2343462..f6aac1761 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
@@ -64,15 +64,15 @@ def macroop BSWAP_D_R
def macroop BSWAP_Q_R
{
roli reg, reg, 8, dataSize=2
- roli reg, reg, 16, dataSize=4
- roli reg, reg, 8, dataSize=2
- roli reg, reg, 32, dataSize=8
- roli reg, reg, 8, dataSize=2
- roli reg, reg, 16, dataSize=4
- roli reg, reg, 8, dataSize=2
+ roli t1, reg, 16, dataSize=4
+ # Top 4 bytes of t1 are now zero
+ roli t1, t1, 8, dataSize=2
+ roli t1, t1, 32, dataSize=8
+ srli t2, reg, 32, dataSize=8
+ roli t2, t2, 8, dataSize=2
+ roli t2, t2, 16, dataSize=4
+ # Top 4 bytes of t2 are now zero
+ roli t2, t2, 8, dataSize=2
+ or reg, t1, t2, dataSize=8
};
'''
-#let {{
-# class BSWAP(Inst):
-# "GenFault ${new UnimpInstFault}"
-#}};