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authorLena Olson <lena@cs.wisc,edu>2013-08-19 03:52:35 -0400
committerLena Olson <lena@cs.wisc,edu>2013-08-19 03:52:35 -0400
commit646c4a23ca44aab5468c896034288151c89be782 (patch)
treee63c57a515669a9c7c24b39b8cfcf39804d00276 /src
parentc26911013c799d63dfe854de8cce11137324cde2 (diff)
downloadgem5-646c4a23ca44aab5468c896034288151c89be782.tar.xz
cpu: Accurately count idle cycles for simple cpu
Added a couple missing updates to the notIdleFraction stat. Without these, it sometimes gives a (not) idle fraction that is greater than 1 or less than 0.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/ozone/cpu_impl.hh4
-rw-r--r--src/cpu/simple/atomic.cc6
-rw-r--r--src/cpu/simple/timing.cc6
3 files changed, 10 insertions, 6 deletions
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index fe8ae2551..f64f287ea 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -282,7 +282,7 @@ OzoneCPU<Impl>::activateContext(int thread_num, int delay)
assert(thread_num == 0);
assert(_status == Idle);
- notIdleFraction++;
+ notIdleFraction = 1;
scheduleTickEvent(delay);
_status = Running;
if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
@@ -300,7 +300,7 @@ OzoneCPU<Impl>::suspendContext(int thread_num)
// @todo: Figure out how to initially set the status properly so
// this is running.
// assert(_status == Running);
- notIdleFraction--;
+ notIdleFraction = 0;
unscheduleTickEvent();
_status = Idle;
}
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ffd1c4d43..d29903c2f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -175,8 +175,10 @@ AtomicSimpleCPU::drainResume()
if (thread->status() == ThreadContext::Active) {
schedule(tickEvent, nextCycle());
_status = BaseSimpleCPU::Running;
+ notIdleFraction = 1;
} else {
_status = BaseSimpleCPU::Idle;
+ notIdleFraction = 0;
}
system->totalNumInsts = 0;
@@ -244,7 +246,7 @@ AtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
assert(_status == Idle);
assert(!tickEvent.scheduled());
- notIdleFraction++;
+ notIdleFraction = 1;
numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
//Make sure ticks are still on multiples of cycles
@@ -271,7 +273,7 @@ AtomicSimpleCPU::suspendContext(ThreadID thread_num)
if (tickEvent.scheduled())
deschedule(tickEvent);
- notIdleFraction--;
+ notIdleFraction = 0;
_status = Idle;
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 075d05d81..744bf8397 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -143,8 +143,10 @@ TimingSimpleCPU::drainResume()
if (thread->status() == ThreadContext::Active) {
schedule(fetchEvent, nextCycle());
_status = BaseSimpleCPU::Running;
+ notIdleFraction = 1;
} else {
_status = BaseSimpleCPU::Idle;
+ notIdleFraction = 0;
}
}
@@ -206,7 +208,7 @@ TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
assert(_status == Idle);
- notIdleFraction++;
+ notIdleFraction = 1;
_status = BaseSimpleCPU::Running;
// kick things off by initiating the fetch of the next instruction
@@ -230,7 +232,7 @@ TimingSimpleCPU::suspendContext(ThreadID thread_num)
// just change status to Idle... if status != Running,
// completeInst() will not initiate fetch of next instruction.
- notIdleFraction--;
+ notIdleFraction = 0;
_status = Idle;
}