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| author | Anouk Van Laer <anouk.vanlaer@arm.com> | 2018-09-03 12:17:27 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-16 11:20:26 +0000 |
| commit | 671840615bb721b9545789555e796f5d47a15bf6 (patch) | |
| tree | ad3b159fd6ae31b932e06f02051cfd2a3ccf9402 /src | |
| parent | b47b123b32d8125ed0e797f4ae8104f69cce1df7 (diff) | |
| download | gem5-671840615bb721b9545789555e796f5d47a15bf6.tar.xz | |
arch-arm: Added TLBI_ALL EL2 instruction
This patch is adding TLBI_ALLE2(IS) operations to the arm ISA.
Change-Id: I8e35cff9a2cc414f4c5fbbc5aa0cfe5023a3f011
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15616
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa.cc | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d7d51b887..17c87ba84 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1338,9 +1338,17 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) tlbiOp.broadcast(tc); return; } - // @todo: uncomment this to enable Virtualization - // case MISCREG_TLBI_ALLE2IS: - // case MISCREG_TLBI_ALLE2: + // AArch64 TLB Invalidate All, EL2, Inner Shareable + case MISCREG_TLBI_ALLE2: + case MISCREG_TLBI_ALLE2IS: + { + assert64(tc); + scr = readMiscReg(MISCREG_SCR, tc); + + TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); + tlbiOp(tc); + return; + } // AArch64 TLB Invalidate All, EL1 case MISCREG_TLBI_ALLE1: case MISCREG_TLBI_VMALLE1: |