*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b

68 files changed, 718 insertions, 718 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 8d13511ac..ec5090eb8 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -62,7 +62,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
 
     AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
 
-    tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
+    tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
     tc->setNextPC(tc->readPC() + sizeof(MachInst));
 
     delete reset;
@@ -76,12 +76,12 @@ void
 AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
 {
     for (int i = 0; i < NumInternalProcRegs; ++i) {
-        tc->setMiscReg(i, 0);
+        tc->setMiscRegNoEffect(i, 0);
     }
 
-    tc->setMiscReg(IPR_PAL_BASE, PalBase);
-    tc->setMiscReg(IPR_MCSR, 0x6);
-    tc->setMiscReg(IPR_PALtemp16, cpuId);
+    tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
+    tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
+    tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
 }
 
 
@@ -94,13 +94,13 @@ AlphaISA::processInterrupts(CPU *cpu)
     int ipl = 0;
     int summary = 0;
 
-    if (cpu->readMiscReg(IPR_ASTRR))
+    if (cpu->readMiscRegNoEffect(IPR_ASTRR))
         panic("asynchronous traps not implemented\n");
 
-    if (cpu->readMiscReg(IPR_SIRR)) {
+    if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
         for (int i = INTLEVEL_SOFTWARE_MIN;
              i < INTLEVEL_SOFTWARE_MAX; i++) {
-            if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+            if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
                 // See table 4-19 of the 21164 hardware reference
                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                 summary |= (ULL(1) << i);
@@ -121,12 +121,12 @@ AlphaISA::processInterrupts(CPU *cpu)
         }
     }
 
-    if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
-        cpu->setMiscReg(IPR_ISR, summary);
-        cpu->setMiscReg(IPR_INTID, ipl);
+    if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
+        cpu->setMiscRegNoEffect(IPR_ISR, summary);
+        cpu->setMiscRegNoEffect(IPR_INTID, ipl);
         cpu->trap(new InterruptFault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                cpu->readMiscReg(IPR_IPLR), ipl, summary);
+                cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
     }
 
 }
@@ -148,7 +148,7 @@ SimpleThread::hwrei()
     if (!(readPC() & 0x3))
         return new UnimplementedOpcodeFault;
 
-    setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
+    setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
 
     if (!misspeculating()) {
         if (kernelStats)
@@ -554,7 +554,7 @@ void
 AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
 {
     for (int i = 0; i < NumInternalProcRegs; ++i) {
-        dest->setMiscReg(i, src->readMiscReg(i));
+        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
     }
 }
 
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 5efcf92e4..9a8429635 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -126,15 +126,15 @@ void AlphaFault::invoke(ThreadContext * tc)
 
     // exception restart address
     if (setRestartAddress() || !(tc->readPC() & 0x3))
-        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
+        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
 
     if (skipFaultingInstruction()) {
         // traps...  skip faulting instruction.
-        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
-                   tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
+        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
+                   tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
     }
 
-    tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
+    tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
     tc->setNextPC(tc->readPC() + sizeof(MachInst));
 }
 
@@ -154,17 +154,17 @@ void DtbFault::invoke(ThreadContext * tc)
     if (!tc->misspeculating()
         && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
         // set VA register with faulting address
-        tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
+        tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
 
         // set MM_STAT register flags
-        tc->setMiscReg(AlphaISA::IPR_MM_STAT,
+        tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
             (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
              | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
              | (flags & 0x3f)));
 
         // set VA_FORM register with faulting formatted address
-        tc->setMiscReg(AlphaISA::IPR_VA_FORM,
-            tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
+        tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
+            tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
     }
 
     AlphaFault::invoke(tc);
@@ -173,9 +173,9 @@ void DtbFault::invoke(ThreadContext * tc)
 void ItbFault::invoke(ThreadContext * tc)
 {
     if (!tc->misspeculating()) {
-        tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
-        tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
-                       tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
+        tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
+        tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
+                       tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
                        (AlphaISA::VAddr(pc).vpn() << 3));
     }
 
diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc
index 0f6806319..f0f1eab7a 100644
--- a/src/arch/alpha/idle_event.cc
+++ b/src/arch/alpha/idle_event.cc
@@ -40,6 +40,6 @@ IdleStartEvent::process(ThreadContext *tc)
 {
     if (tc->getKernelStats())
         tc->getKernelStats()->setIdleProcess(
-            tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc);
+            tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23), tc);
     remove();
 }
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 0500714ad..6453edf97 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -112,13 +112,13 @@ namespace AlphaISA
             int ipl = 0;
             int summary = 0;
 
-            if (tc->readMiscReg(IPR_ASTRR))
+            if (tc->readMiscRegNoEffect(IPR_ASTRR))
                 panic("asynchronous traps not implemented\n");
 
-            if (tc->readMiscReg(IPR_SIRR)) {
+            if (tc->readMiscRegNoEffect(IPR_SIRR)) {
                 for (int i = INTLEVEL_SOFTWARE_MIN;
                      i < INTLEVEL_SOFTWARE_MAX; i++) {
-                    if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+                    if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
                         // See table 4-19 of 21164 hardware reference
                         ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                         summary |= (ULL(1) << i);
@@ -138,12 +138,12 @@ namespace AlphaISA
                 }
             }
 
-            if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
+            if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
                 newIpl = ipl;
                 newSummary = summary;
                 newInfoSet = true;
                 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                        tc->readMiscReg(IPR_IPLR), ipl, summary);
+                        tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
 
                 return new InterruptFault;
             } else {
@@ -154,8 +154,8 @@ namespace AlphaISA
         void updateIntrInfo(ThreadContext *tc)
         {
             assert(newInfoSet);
-            tc->setMiscReg(IPR_ISR, newSummary);
-            tc->setMiscReg(IPR_INTID, newIpl);
+            tc->setMiscRegNoEffect(IPR_ISR, newSummary);
+            tc->setMiscRegNoEffect(IPR_INTID, newIpl);
             newInfoSet = false;
         }
 
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 49c25c3c2..b62372f66 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -638,7 +638,7 @@ decode OPCODE default Unknown::unknown() {
         /* Rb is a fake dependency so here is a fun way to get
          * the parser to understand that.
          */
-                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0);
+                Ra = xc->readMiscReg(AlphaISA::IPR_CC) + (Rb & 0);
 
 #else
                 Ra = curTick;
@@ -690,7 +690,7 @@ decode OPCODE default Unknown::unknown() {
     0x00: CallPal::call_pal({{
         if (!palValid ||
             (palPriv
-             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
+             && xc->readMiscReg(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
             fault = new UnimplementedOpcodeFault;
@@ -701,8 +701,8 @@ decode OPCODE default Unknown::unknown() {
             bool dopal = xc->simPalCheck(palFunc);
 
             if (dopal) {
-                xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
-                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset;
+                xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, NPC);
+                NPC = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + palOffset;
             }
         }
     }}, IsNonSpeculative);
@@ -760,7 +760,7 @@ decode OPCODE default Unknown::unknown() {
                     miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
-                    Ra = xc->readMiscRegWithEffect(miscRegIndex);
+                    Ra = xc->readMiscReg(miscRegIndex);
             }}, IsIprAccess);
         }
     }
@@ -775,7 +775,7 @@ decode OPCODE default Unknown::unknown() {
                     miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
-                    xc->setMiscRegWithEffect(miscRegIndex, Ra);
+                    xc->setMiscReg(miscRegIndex, Ra);
                 if (traceData) { traceData->setData(Ra); }
             }}, IsIprAccess);
         }
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index c845ea442..a350aa05f 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
-        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
+        if (!EV5::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
@@ -229,7 +229,7 @@ def template FloatingPointExecute {{
             %(code)s;
         } else {
             fesetround(getC99RoundingMode(
-                           xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
+                           xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
             %(code)s;
             fesetround(FE_TONEAREST);
         }
diff --git a/src/arch/alpha/kernel_stats.cc b/src/arch/alpha/kernel_stats.cc
index 6fc3cb72f..13dc95af7 100644
--- a/src/arch/alpha/kernel_stats.cc
+++ b/src/arch/alpha/kernel_stats.cc
@@ -150,7 +150,7 @@ Statistics::changeMode(cpu_mode newmode, ThreadContext *tc)
 void
 Statistics::mode(cpu_mode newmode, ThreadContext *tc)
 {
-    Addr pcbb = tc->readMiscReg(AlphaISA::IPR_PALtemp23);
+    Addr pcbb = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23);
 
     if (newmode == kernel && pcbb == idleProcess)
         newmode = idle;
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 56b5ba5ed..df66b92bc 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -56,8 +56,8 @@ template <class XC>
 inline void
 handleLockedRead(XC *xc, Request *req)
 {
-    xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
-    xc->setMiscReg(MISCREG_LOCKFLAG, true);
+    xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
+    xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true);
 }
 
 
@@ -71,13 +71,13 @@ handleLockedWrite(XC *xc, Request *req)
         req->setExtraData(2);
     } else {
         // standard store conditional
-        bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
-        Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
+        bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG);
+        Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR);
         if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
             // Lock flag not set or addr mismatch in CPU;
             // don't even bother sending to memory system
             req->setExtraData(0);
-            xc->setMiscReg(MISCREG_LOCKFLAG, false);
+            xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false);
             // the rest of this code is not architectural;
             // it's just a debugging aid to help detect
             // livelock by warning on long sequences of failed
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 67f6c98e4..1af97adcf 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -61,7 +61,7 @@ namespace AlphaISA
     }
 
     MiscReg
-    MiscRegFile::readReg(int misc_reg)
+    MiscRegFile::readRegNoEffect(int misc_reg)
     {
         switch(misc_reg) {
           case MISCREG_FPCR:
@@ -87,7 +87,7 @@ namespace AlphaISA
     }
 
     MiscReg
-    MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc)
+    MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
     {
         switch(misc_reg) {
           case MISCREG_FPCR:
@@ -112,7 +112,7 @@ namespace AlphaISA
     }
 
     void
-    MiscRegFile::setReg(int misc_reg, const MiscReg &val)
+    MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val)
     {
         switch(misc_reg) {
           case MISCREG_FPCR:
@@ -143,7 +143,7 @@ namespace AlphaISA
     }
 
     void
-    MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val,
+    MiscRegFile::setReg(int misc_reg, const MiscReg &val,
             ThreadContext *tc)
     {
         switch(misc_reg) {
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index 31b3e59b3..aea702849 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -75,18 +75,18 @@ namespace AlphaISA
 #endif
         }
 
-        MiscReg readReg(int misc_reg);
+        MiscReg readRegNoEffect(int misc_reg);
 
-        MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
+        MiscReg readReg(int misc_reg, ThreadContext *tc);
 
         //These functions should be removed once the simplescalar cpu model
         //has been replaced.
         int getInstAsid();
         int getDataAsid();
 
-        void setReg(int misc_reg, const MiscReg &val);
+        void setRegNoEffect(int misc_reg, const MiscReg &val);
 
-        void setRegWithEffect(int misc_reg, const MiscReg &val,
+        void setReg(int misc_reg, const MiscReg &val,
                 ThreadContext *tc);
 
         void clear()
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index 92e1b07df..3b42ca9bc 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -85,14 +85,14 @@ namespace AlphaISA
     void
     copyMiscRegs(ThreadContext *src, ThreadContext *dest)
     {
-        dest->setMiscReg(AlphaISA::MISCREG_FPCR,
-                src->readMiscReg(AlphaISA::MISCREG_FPCR));
-        dest->setMiscReg(AlphaISA::MISCREG_UNIQ,
-                src->readMiscReg(AlphaISA::MISCREG_UNIQ));
-        dest->setMiscReg(AlphaISA::MISCREG_LOCKFLAG,
-                src->readMiscReg(AlphaISA::MISCREG_LOCKFLAG));
-        dest->setMiscReg(AlphaISA::MISCREG_LOCKADDR,
-                src->readMiscReg(AlphaISA::MISCREG_LOCKADDR));
+        dest->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR,
+                src->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR));
+        dest->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ,
+                src->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ));
+        dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG,
+                src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG));
+        dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR,
+                src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR));
 
 #if FULL_SYSTEM
         copyIprs(src, dest);
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 54372da36..b93707181 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -106,25 +106,25 @@ namespace AlphaISA
             miscRegFile.clear();
         }
 
-        MiscReg readMiscReg(int miscReg)
+        MiscReg readMiscRegNoEffect(int miscReg)
         {
-            return miscRegFile.readReg(miscReg);
+            return miscRegFile.readRegNoEffect(miscReg);
         }
 
-        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc)
         {
-            return miscRegFile.readRegWithEffect(miscReg, tc);
+            return miscRegFile.readReg(miscReg, tc);
         }
 
-        void setMiscReg(int miscReg, const MiscReg &val)
+        void setMiscRegNoEffect(int miscReg, const MiscReg &val)
         {
-            miscRegFile.setReg(miscReg, val);
+            miscRegFile.setRegNoEffect(miscReg, val);
         }
 
-        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscReg(int miscReg, const MiscReg &val,
                 ThreadContext * tc)
         {
-            miscRegFile.setRegWithEffect(miscReg, val, tc);
+            miscRegFile.setReg(miscReg, val, tc);
         }
 
         FloatReg readFloatReg(int floatReg)
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index 4637bd7a6..a68e5218e 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -187,7 +187,7 @@ RemoteGDB::acc(Addr va, size_t len)
         if (AlphaISA::PcPAL(va) || va < 0x10000)
             return true;
 
-        Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20);
+        Addr ptbr = context->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20);
         TheISA::PageTableEntry pte = TheISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va);
         if (!pte.valid()) {
             DPRINTF(GDBAcc, "acc:   %#x pte is invalid\n", va);
diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc
index c4612e156..c16498e72 100644
--- a/src/arch/alpha/stacktrace.cc
+++ b/src/arch/alpha/stacktrace.cc
@@ -146,7 +146,7 @@ namespace AlphaISA
     {
         tc = _tc;
 
-        bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+        bool usermode = (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
 
         Addr pc = tc->readNextPC();
         bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
@@ -219,22 +219,22 @@ namespace AlphaISA
     bool
     StackTrace::isEntry(Addr addr)
     {
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp12))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp7))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp11))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp21))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp9))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp2))
             return true;
 
         return false;
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 1e0155138..3ab65e664 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -312,14 +312,14 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const
         // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
         // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
 #if ALPHA_TLASER
-        if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
+        if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
             VAddrSpaceEV5(req->getVaddr()) == 2)
 #else
         if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
 #endif
         {
             // only valid in kernel mode
-            if (ICM_CM(tc->readMiscReg(IPR_ICM)) !=
+            if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
                 mode_kernel) {
                 acv++;
                 return new ItbAcvFault(req->getVaddr());
@@ -337,7 +337,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const
 
         } else {
             // not a physical address: need to look up pte
-            int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
+            int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
             PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
                               asn);
 
@@ -352,7 +352,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const
 
             // check permissions for this access
             if (!(pte->xre &
-                  (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) {
+                  (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
                 // instruction access fault
                 acv++;
                 return new ItbAcvFault(req->getVaddr());
@@ -453,7 +453,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
     Addr pc = tc->readPC();
 
     mode_type mode =
-        (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM));
+        (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
 
 
     /**
@@ -469,7 +469,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
     if (PcPAL(pc)) {
         mode = (req->getFlags() & ALTMODE) ?
             (mode_type)ALT_MODE_AM(
-                tc->readMiscReg(IPR_ALT_MODE))
+                tc->readMiscRegNoEffect(IPR_ALT_MODE))
             : mode_kernel;
     }
 
@@ -487,7 +487,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
 
         // Check for "superpage" mapping
 #if ALPHA_TLASER
-        if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
+        if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
             VAddrSpaceEV5(req->getVaddr()) == 2)
 #else
         if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
@@ -495,7 +495,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
         {
 
             // only valid in kernel mode
-            if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) !=
+            if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
                 mode_kernel) {
                 if (write) { write_acv++; } else { read_acv++; }
                 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
@@ -519,7 +519,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
             else
                 read_accesses++;
 
-            int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
+            int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
 
             // not a physical address: need to look up pte
             PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 9a06cc2a4..c8a50e8a2 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -45,7 +45,7 @@ namespace AlphaISA
     static inline bool
     inUserMode(ThreadContext *tc)
     {
-        return (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+        return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
     }
 
     static inline ExtMachInst
diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc
index 1a3147bcc..6ffbea181 100644
--- a/src/arch/alpha/vtophys.cc
+++ b/src/arch/alpha/vtophys.cc
@@ -88,7 +88,7 @@ Addr
 AlphaISA::vtophys(ThreadContext *tc, Addr addr)
 {
     AlphaISA::VAddr vaddr = addr;
-    Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20);
+    Addr ptbr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20);
     Addr paddr = 0;
     //@todo Andrew couldn't remember why he commented some of this code
     //so I put it back in. Perhaps something to do with gdb debugging?
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 3a8688797..b5d1df4fc 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -289,8 +289,8 @@ decode OPCODE_HI default Unknown::unknown() {
         0x0: decode RS_MSB {
             0x0: decode RS {
                 format CP0Control {
-                    0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }});
-                    0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }});
+                    0x0: mfc0({{ Rt = xc->readMiscRegNoEffect(RD << 5 | SEL); }});
+                    0x4: mtc0({{ xc->setMiscRegNoEffect(RD << 5 | SEL, Rt); }});
                 }
 
                 format MipsMT {
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 368925e00..53ee09512 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -215,22 +215,22 @@ namespace MipsISA
 
         void copyMiscRegs(ThreadContext *tc);
 
-        MiscReg readReg(int misc_reg)
+        MiscReg readRegNoEffect(int misc_reg)
         {
             return miscRegFile[misc_reg];
         }
 
-        MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc)
+        MiscReg readReg(int misc_reg, ThreadContext *tc)
         {
             return miscRegFile[misc_reg];
         }
 
-        void setReg(int misc_reg, const MiscReg &val)
+        void setRegNoEffect(int misc_reg, const MiscReg &val)
         {
             miscRegFile[misc_reg] = val;
         }
 
-        void setRegWithEffect(int misc_reg, const MiscReg &val,
+        void setReg(int misc_reg, const MiscReg &val,
                                ThreadContext *tc)
         {
             miscRegFile[misc_reg] = val;
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 7b57b31f5..387fbd5c8 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -57,25 +57,25 @@ namespace MipsISA
             bzero(&miscRegFile, sizeof(miscRegFile));
         }
 
-        MiscReg readMiscReg(int miscReg)
+        MiscReg readMiscRegNoEffect(int miscReg)
         {
-            return miscRegFile.readReg(miscReg);
+            return miscRegFile.readRegNoEffect(miscReg);
         }
 
-        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc)
         {
-            return miscRegFile.readRegWithEffect(miscReg, tc);
+            return miscRegFile.readReg(miscReg, tc);
         }
 
-        void setMiscReg(int miscReg, const MiscReg &val)
+        void setMiscRegNoEffect(int miscReg, const MiscReg &val)
         {
-            miscRegFile.setReg(miscReg, val);
+            miscRegFile.setRegNoEffect(miscReg, val);
         }
 
-        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscReg(int miscReg, const MiscReg &val,
                 ThreadContext * tc)
         {
-            miscRegFile.setRegWithEffect(miscReg, val, tc);
+            miscRegFile.setReg(miscReg, val, tc);
         }
 
         FloatRegVal readFloatReg(int floatReg)
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index b1a6ae919..f6cf97872 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -282,17 +282,17 @@ void enterREDState(ThreadContext *tc)
 {
     //@todo Disable the mmu?
     //@todo Disable watchpoints?
-    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
+    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
     //HPSTATE.red = 1
     HPSTATE |= (1 << 5);
     //HPSTATE.hpriv = 1
     HPSTATE |= (1 << 2);
-    tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
+    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
     //PSTATE.priv is set to 1 here. The manual says it should be 0, but
     //Legion sets it to 1.
-    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
+    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
     PSTATE |= (1 << 2);
-    tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
+    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
 }
 
 /**
@@ -302,17 +302,17 @@ void enterREDState(ThreadContext *tc)
 
 void doREDFault(ThreadContext *tc, TrapType tt)
 {
-    MiscReg TL = tc->readMiscReg(MISCREG_TL);
-    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
-    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
-    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
-    //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
+    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
+    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
+    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
+    //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
     MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
-    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
-    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
-    //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
-    MiscReg CANSAVE = tc->readMiscReg(NumIntArchRegs + 3);
-    MiscReg GL = tc->readMiscReg(MISCREG_GL);
+    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
+    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
+    //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
+    MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
+    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
     MiscReg PC = tc->readPC();
     MiscReg NPC = tc->readNextPC();
 
@@ -335,25 +335,25 @@ void doREDFault(ThreadContext *tc, TrapType tt)
     replaceBits(TSTATE, 4, 0, CWP);
 
     //Write back TSTATE
-    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
+    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
 
     //set TPC to PC
-    tc->setMiscReg(MISCREG_TPC, PC);
+    tc->setMiscRegNoEffect(MISCREG_TPC, PC);
     //set TNPC to NPC
-    tc->setMiscReg(MISCREG_TNPC, NPC);
+    tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
 
     //set HTSTATE.hpstate to hpstate
-    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
+    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
 
     //TT = trap type;
-    tc->setMiscReg(MISCREG_TT, tt);
+    tc->setMiscRegNoEffect(MISCREG_TT, tt);
 
     //Update GL
-    tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
+    tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
 
     PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
     PSTATE |= (1 << 4); //set PSTATE.pef to 1
-    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
+    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
 
     //set HPSTATE.red to 1
     HPSTATE |= (1 << 5);
@@ -363,7 +363,7 @@ void doREDFault(ThreadContext *tc, TrapType tt)
     HPSTATE &= ~(1 << 10);
     //set HPSTATE.tlz to 0
     HPSTATE &= ~(1 << 0);
-    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
+    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
 
     bool changedCWP = true;
     if(tt == 0x24)
@@ -378,7 +378,7 @@ void doREDFault(ThreadContext *tc, TrapType tt)
     if(changedCWP)
     {
         CWP = (CWP + NWindows) % NWindows;
-        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
+        tc->setMiscReg(MISCREG_CWP, CWP);
     }
 }
 
@@ -389,17 +389,17 @@ void doREDFault(ThreadContext *tc, TrapType tt)
 
 void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
 {
-    MiscReg TL = tc->readMiscReg(MISCREG_TL);
-    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
-    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
-    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
-    //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
+    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
+    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
+    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
+    //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
     MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
-    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
-    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
-    //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
+    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
+    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
+    //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
     MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
-    MiscReg GL = tc->readMiscReg(MISCREG_GL);
+    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
     MiscReg PC = tc->readPC();
     MiscReg NPC = tc->readNextPC();
 
@@ -410,7 +410,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
 
     //Increment the trap level
     TL++;
-    tc->setMiscReg(MISCREG_TL, TL);
+    tc->setMiscRegNoEffect(MISCREG_TL, TL);
 
     //Save off state
 
@@ -426,24 +426,24 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
     replaceBits(TSTATE, 4, 0, CWP);
 
     //Write back TSTATE
-    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
+    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
 
     //set TPC to PC
-    tc->setMiscReg(MISCREG_TPC, PC);
+    tc->setMiscRegNoEffect(MISCREG_TPC, PC);
     //set TNPC to NPC
-    tc->setMiscReg(MISCREG_TNPC, NPC);
+    tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
 
     //set HTSTATE.hpstate to hpstate
-    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
+    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
 
     //TT = trap type;
-    tc->setMiscReg(MISCREG_TT, tt);
+    tc->setMiscRegNoEffect(MISCREG_TT, tt);
 
     //Update the global register level
     if (!gotoHpriv)
-        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
+        tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxPGL));
     else
-        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
+        tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
 
     //PSTATE.mm is unchanged
     PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
@@ -460,12 +460,12 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
         HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
         HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
         //HPSTATE.tlz is unchanged
-        tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
+        tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
     } else { // we are going to priv
         PSTATE |= (1 << 2); //PSTATE.priv = 1
         replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
     }
-    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
+    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
 
 
     bool changedCWP = true;
@@ -481,7 +481,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
     if (changedCWP)
     {
         CWP = (CWP + NWindows) % NWindows;
-        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
+        tc->setMiscReg(MISCREG_CWP, CWP);
     }
 }
 
@@ -495,14 +495,14 @@ void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
 
 void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
 {
-    Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
+    Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
     PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
     NPC = PC + sizeof(MachInst);
 }
 
 void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
 {
-    Addr TBA = tc->readMiscReg(MISCREG_TBA);
+    Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
     PC = (TBA & ~mask(15)) |
         (TL > 1 ? (1 << 14) : 0) |
         ((TT << 5) & mask(14));
@@ -519,10 +519,10 @@ void SparcFaultBase::invoke(ThreadContext * tc)
 
     //We can refer to this to see what the trap level -was-, but something
     //in the middle could change it in the regfile out from under us.
-    MiscReg tl = tc->readMiscReg(MISCREG_TL);
-    MiscReg tt = tc->readMiscReg(MISCREG_TT);
-    MiscReg pstate = tc->readMiscReg(MISCREG_PSTATE);
-    MiscReg hpstate = tc->readMiscReg(MISCREG_HPSTATE);
+    MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
+    MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
+    MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+    MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
 
     Addr PC, NPC;
 
@@ -571,15 +571,15 @@ void PowerOnReset::invoke(ThreadContext * tc)
     //on reset Trap which sets the processor into the following state.
     //Bits that aren't set aren't defined on startup.
 
-    tc->setMiscReg(MISCREG_TL, MaxTL);
-    tc->setMiscReg(MISCREG_TT, trapType());
-    tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
+    tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
+    tc->setMiscRegNoEffect(MISCREG_TT, trapType());
+    tc->setMiscReg(MISCREG_GL, MaxGL);
 
     //Turn on pef and priv, set everything else to 0
-    tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
+    tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2));
 
     //Turn on red and hpriv, set everything else to 0
-    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
+    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
     //HPSTATE.red = 1
     HPSTATE |= (1 << 5);
     //HPSTATE.hpriv = 1
@@ -588,10 +588,10 @@ void PowerOnReset::invoke(ThreadContext * tc)
     HPSTATE &= ~(1 << 10);
     //HPSTATE.tlz = 0
     HPSTATE &= ~(1 << 0);
-    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
+    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
 
     //The tick register is unreadable by nonprivileged software
-    tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
+    tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
 
     //Enter RED state. We do this last so that the actual state preserved in
     //the trap stack is the state from before this fault.
@@ -609,7 +609,7 @@ void PowerOnReset::invoke(ThreadContext * tc)
     // Clear all the soft interrupt bits
     softint = 0;
     // disable timer compare interrupts, reset tick_cmpr
-    tc->setMiscReg(MISCREG_
+    tc->setMiscRegNoEffect(MISCREG_
     tick_cmprFields.int_dis = 1;
     tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
     stickFields.npt = 1; //The TICK register is unreadable by by !priv
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index 3234002c5..4ad3385fb 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -102,8 +102,8 @@ class Interrupts
 
     Fault getInterrupt(ThreadContext * tc)
     {
-        int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
-        int pstate = tc->readMiscReg(MISCREG_PSTATE);
+        int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
+        int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
         bool ie = pstate & PSTATE::ie;
 
         // THESE ARE IN ORDER OF PRIORITY
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 693cc6876..bba63f407 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -492,8 +492,8 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
-        if (xc->readMiscRegWithEffect(MISCREG_PSTATE) & PSTATE::pef &&
-            xc->readMiscRegWithEffect(MISCREG_FPRS) & 0x4)
+        if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
+            xc->readMiscReg(MISCREG_FPRS) & 0x4)
             return NoFault;
         else
             return new FpDisabled;
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 849eed1cc..e7b866e6f 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -140,7 +140,7 @@ void MiscRegFile::clear()
 #endif
 }
 
-MiscReg MiscRegFile::readReg(int miscReg)
+MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 {
     switch (miscReg) {
       case MISCREG_TLB_DATA:
@@ -331,7 +331,7 @@ MiscReg MiscRegFile::readReg(int miscReg)
     }
 }
 
-MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
+MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 {
     switch (miscReg) {
         // tick and stick are aliased to each other in niagra
@@ -386,10 +386,10 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 #endif
 
     }
-    return readReg(miscReg);
+    return readRegNoEffect(miscReg);
 }
 
-void MiscRegFile::setReg(int miscReg, const MiscReg &val)
+void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 {
     switch (miscReg) {
 //      case MISCREG_Y:
@@ -621,7 +621,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
     }
 }
 
-void MiscRegFile::setRegWithEffect(int miscReg,
+void MiscRegFile::setReg(int miscReg,
         const MiscReg &val, ThreadContext * tc)
 {
     MiscReg new_val = val;
@@ -692,7 +692,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
       panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
 #endif
     }
-    setReg(miscReg, new_val);
+    setRegNoEffect(miscReg, new_val);
 }
 
 void MiscRegFile::serialize(std::ostream & os)
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index ac0e930c5..cb46eb2aa 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -291,13 +291,13 @@ namespace SparcISA
             clear();
         }
 
-        MiscReg readReg(int miscReg);
+        MiscReg readRegNoEffect(int miscReg);
 
-        MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
+        MiscReg readReg(int miscReg, ThreadContext *tc);
 
-        void setReg(int miscReg, const MiscReg &val);
+        void setRegNoEffect(int miscReg, const MiscReg &val);
 
-        void setRegWithEffect(int miscReg,
+        void setReg(int miscReg,
                 const MiscReg &val, ThreadContext * tc);
 
         int getInstAsid()
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index c3b833562..a6cefa080 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -88,38 +88,38 @@ Sparc32LiveProcess::startup()
     //From the SPARC ABI
 
     //The process runs in user mode
-    threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
+    threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02);
 
     //Setup default FP state
-    threadContexts[0]->setMiscReg(MISCREG_FSR, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);
 
-    threadContexts[0]->setMiscReg(MISCREG_TICK, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0);
     //
     /*
      * Register window management registers
      */
 
     //No windows contain info from other programs
-    //threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0);
     //There are no windows to pop
-    //threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0);
     //All windows are available to save into
-    //threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
     threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2);
     //All windows are "clean"
-    //threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
     threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows);
     //Start with register window 0
-    threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0);
     //Always use spill and fill traps 0
-    //threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
     //Set the trap level to 0
-    threadContexts[0]->setMiscReg(MISCREG_TL, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
     //Set the ASI register to something fixed
-    threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
 }
 
 void
@@ -130,38 +130,38 @@ Sparc64LiveProcess::startup()
     //From the SPARC ABI
 
     //The process runs in user mode
-    threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
+    threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02);
 
     //Setup default FP state
-    threadContexts[0]->setMiscReg(MISCREG_FSR, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);
 
-    threadContexts[0]->setMiscReg(MISCREG_TICK, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0);
     //
     /*
      * Register window management registers
      */
 
     //No windows contain info from other programs
-    //threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0);
     //There are no windows to pop
-    //threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0);
     //All windows are available to save into
-    //threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
     threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2);
     //All windows are "clean"
-    //threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
     threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows);
     //Start with register window 0
-    threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0);
     //Always use spill and fill traps 0
-    //threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
     //Set the trap level to 0
-    threadContexts[0]->setMiscReg(MISCREG_TL, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
     //Set the ASI register to something fixed
-    threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
 }
 
 M5_32_auxv_t::M5_32_auxv_t(int32_t type, int32_t val)
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 944b1f401..667b1f002 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -75,25 +75,25 @@ void RegFile::clear()
     miscRegFile.clear();
 }
 
-MiscReg RegFile::readMiscReg(int miscReg)
+MiscReg RegFile::readMiscRegNoEffect(int miscReg)
 {
-    return miscRegFile.readReg(miscReg);
+    return miscRegFile.readRegNoEffect(miscReg);
 }
 
-MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
+MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
 {
-    return miscRegFile.readRegWithEffect(miscReg, tc);
+    return miscRegFile.readReg(miscReg, tc);
 }
 
-void RegFile::setMiscReg(int miscReg, const MiscReg &val)
+void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
 {
-    miscRegFile.setReg(miscReg, val);
+    miscRegFile.setRegNoEffect(miscReg, val);
 }
 
-void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
+void RegFile::setMiscReg(int miscReg, const MiscReg &val,
         ThreadContext * tc)
 {
-    miscRegFile.setRegWithEffect(miscReg, val, tc);
+    miscRegFile.setReg(miscReg, val, tc);
 }
 
 FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -153,8 +153,8 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
 
 int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
 {
-    int gl = tc->readMiscReg(MISCREG_GL);
-    int cwp = tc->readMiscReg(MISCREG_CWP);
+    int gl = tc->readMiscRegNoEffect(MISCREG_GL);
+    int cwp = tc->readMiscRegNoEffect(MISCREG_CWP);
     //DPRINTF(Sparc, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
     int newReg;
     //The total number of global registers
@@ -257,146 +257,146 @@ void RegFile::changeContext(RegContextParam param, RegContextVal val)
 void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
 
-    uint8_t tl = src->readMiscReg(MISCREG_TL);
+    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
 
     // Read all the trap level dependent registers and save them off
     for(int i = 1; i <= MaxTL; i++)
     {
-        src->setMiscReg(MISCREG_TL, i);
-        dest->setMiscReg(MISCREG_TL, i);
+        src->setMiscRegNoEffect(MISCREG_TL, i);
+        dest->setMiscRegNoEffect(MISCREG_TL, i);
 
-        dest->setMiscReg(MISCREG_TT, src->readMiscReg(MISCREG_TT));
-        dest->setMiscReg(MISCREG_TPC, src->readMiscReg(MISCREG_TPC));
-        dest->setMiscReg(MISCREG_TNPC, src->readMiscReg(MISCREG_TNPC));
-        dest->setMiscReg(MISCREG_TSTATE, src->readMiscReg(MISCREG_TSTATE));
+        dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT));
+        dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC));
+        dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC));
+        dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE));
     }
 
     // Save off the traplevel
-    dest->setMiscReg(MISCREG_TL, tl);
-    src->setMiscReg(MISCREG_TL, tl);
+    dest->setMiscRegNoEffect(MISCREG_TL, tl);
+    src->setMiscRegNoEffect(MISCREG_TL, tl);
 
 
     // ASRs
-//    dest->setMiscReg(MISCREG_Y, src->readMiscReg(MISCREG_Y));
-//    dest->setMiscReg(MISCREG_CCR, src->readMiscReg(MISCREG_CCR));
-    dest->setMiscReg(MISCREG_ASI, src->readMiscReg(MISCREG_ASI));
-    dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
-    dest->setMiscReg(MISCREG_FPRS, src->readMiscReg(MISCREG_FPRS));
-    dest->setMiscReg(MISCREG_SOFTINT, src->readMiscReg(MISCREG_SOFTINT));
-    dest->setMiscReg(MISCREG_TICK_CMPR, src->readMiscReg(MISCREG_TICK_CMPR));
-    dest->setMiscReg(MISCREG_STICK, src->readMiscReg(MISCREG_STICK));
-    dest->setMiscReg(MISCREG_STICK_CMPR, src->readMiscReg(MISCREG_STICK_CMPR));
+//    dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
+//    dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
+    dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI));
+    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
+    dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS));
+    dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT));
+    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
+    dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK));
+    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
 
     // Priv Registers
-    dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
-    dest->setMiscReg(MISCREG_TBA, src->readMiscReg(MISCREG_TBA));
-    dest->setMiscReg(MISCREG_PSTATE, src->readMiscReg(MISCREG_PSTATE));
-    dest->setMiscReg(MISCREG_PIL, src->readMiscReg(MISCREG_PIL));
-    dest->setMiscReg(MISCREG_CWP, src->readMiscReg(MISCREG_CWP));
-//    dest->setMiscReg(MISCREG_CANSAVE, src->readMiscReg(MISCREG_CANSAVE));
-//    dest->setMiscReg(MISCREG_CANRESTORE, src->readMiscReg(MISCREG_CANRESTORE));
-//    dest->setMiscReg(MISCREG_OTHERWIN, src->readMiscReg(MISCREG_OTHERWIN));
-//    dest->setMiscReg(MISCREG_CLEANWIN, src->readMiscReg(MISCREG_CLEANWIN));
-//    dest->setMiscReg(MISCREG_WSTATE, src->readMiscReg(MISCREG_WSTATE));
-    dest->setMiscReg(MISCREG_GL, src->readMiscReg(MISCREG_GL));
+    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
+    dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA));
+    dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE));
+    dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL));
+    dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP));
+//    dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
+//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
+//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
+//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
+//    dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
+    dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
 
     // Hyperprivilged registers
-    dest->setMiscReg(MISCREG_HPSTATE, src->readMiscReg(MISCREG_HPSTATE));
-    dest->setMiscReg(MISCREG_HINTP, src->readMiscReg(MISCREG_HINTP));
-    dest->setMiscReg(MISCREG_HTBA, src->readMiscReg(MISCREG_HTBA));
-    dest->setMiscReg(MISCREG_STRAND_STS_REG,
-            src->readMiscReg(MISCREG_STRAND_STS_REG));
-    dest->setMiscReg(MISCREG_HSTICK_CMPR,
-            src->readMiscReg(MISCREG_HSTICK_CMPR));
+    dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE));
+    dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP));
+    dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA));
+    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
+    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
+            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
 
     // FSR
-    dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR));
+    dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR));
 
     //Strand Status Register
-    dest->setMiscReg(MISCREG_STRAND_STS_REG,
-            src->readMiscReg(MISCREG_STRAND_STS_REG));
+    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
 
     // MMU Registers
-    dest->setMiscReg(MISCREG_MMU_P_CONTEXT,
-            src->readMiscReg(MISCREG_MMU_P_CONTEXT));
-    dest->setMiscReg(MISCREG_MMU_S_CONTEXT,
-            src->readMiscReg(MISCREG_MMU_S_CONTEXT));
-    dest->setMiscReg(MISCREG_MMU_PART_ID,
-            src->readMiscReg(MISCREG_MMU_PART_ID));
-    dest->setMiscReg(MISCREG_MMU_LSU_CTRL,
-            src->readMiscReg(MISCREG_MMU_LSU_CTRL));
-
-    dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0,
-            src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
-    dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1,
-            src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
-    dest->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG,
-            src->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
-    dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0,
-            src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
-    dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1,
-            src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
-    dest->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG,
-            src->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
-    dest->setMiscReg(MISCREG_MMU_ITLB_SFSR,
-            src->readMiscReg(MISCREG_MMU_ITLB_SFSR));
-    dest->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
-            src->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
-
-    dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0,
-            src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
-    dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1,
-            src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
-    dest->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG,
-            src->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
-    dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0,
-            src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
-    dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1,
-            src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
-    dest->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG,
-            src->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
-    dest->setMiscReg(MISCREG_MMU_DTLB_SFSR,
-            src->readMiscReg(MISCREG_MMU_DTLB_SFSR));
-    dest->setMiscReg(MISCREG_MMU_DTLB_SFAR,
-            src->readMiscReg(MISCREG_MMU_DTLB_SFAR));
-    dest->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
-            src->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
+    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
+            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
+    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
+            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
+    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
+            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
+    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
+            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
+
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS0,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS1,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_C0_CONFIG,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_C0_CONFIG));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS0,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS1,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_CX_CONFIG,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_CX_CONFIG));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_SFSR,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_SFSR));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_TAG_ACCESS,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
+
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS0,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS1,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_C0_CONFIG,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_C0_CONFIG));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS0,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS1,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_CX_CONFIG,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_CX_CONFIG));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_SFSR,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_SFSR));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_SFAR,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_SFAR));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_TAG_ACCESS,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
 
     // Scratchpad Registers
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R0,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R0));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R1,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R1));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R2,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R2));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R3,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R3));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R4,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R4));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R5,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R5));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R6,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R6));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R7,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R7));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
 
     // Queue Registers
-    dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD,
-            src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD));
-    dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL,
-            src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL));
-    dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD,
-            src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD));
-    dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL,
-            src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL));
-    dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD,
-            src->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD));
-    dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL,
-            src->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL));
-    dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD,
-            src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD));
-    dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL,
-            src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
 }
 
 void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 9e0b3beb3..f3e253f7e 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -73,13 +73,13 @@ namespace SparcISA
 
         int FlattenIntIndex(int reg);
 
-        MiscReg readMiscReg(int miscReg);
+        MiscReg readMiscRegNoEffect(int miscReg);
 
-        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
 
-        void setMiscReg(int miscReg, const MiscReg &val);
+        void setMiscRegNoEffect(int miscReg, const MiscReg &val);
 
-        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscReg(int miscReg, const MiscReg &val,
                 ThreadContext * tc);
 
         int instAsid()
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index e2ea7a84d..85b0c03a3 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -167,7 +167,7 @@ RemoteGDB::getregs()
 {
     memset(gdbregs.regs, 0, gdbregs.size);
 
-    if (context->readMiscRegWithEffect(MISCREG_PSTATE) &
+    if (context->readMiscReg(MISCREG_PSTATE) &
            PSTATE::am) {
         uint32_t *regs;
         regs = (uint32_t*)gdbregs.regs;
@@ -177,8 +177,8 @@ RemoteGDB::getregs()
             regs[x] = htobe((uint32_t)context->readIntReg(x - RegG0));
 
         regs[Reg32Y] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 1));
-        regs[Reg32Psr] = htobe((uint32_t)context->readMiscRegWithEffect(MISCREG_PSTATE));
-        regs[Reg32Fsr] = htobe((uint32_t)context->readMiscRegWithEffect(MISCREG_FSR));
+        regs[Reg32Psr] = htobe((uint32_t)context->readMiscReg(MISCREG_PSTATE));
+        regs[Reg32Fsr] = htobe((uint32_t)context->readMiscReg(MISCREG_FSR));
         regs[Reg32Csr] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 2));
     } else {
         gdbregs.regs[RegPc] = htobe(context->readPC());
@@ -186,13 +186,13 @@ RemoteGDB::getregs()
         for(int x = RegG0; x <= RegI0 + 7; x++)
             gdbregs.regs[x] = htobe(context->readIntReg(x - RegG0));
 
-        gdbregs.regs[RegFsr] = htobe(context->readMiscRegWithEffect(MISCREG_FSR));
-        gdbregs.regs[RegFprs] = htobe(context->readMiscRegWithEffect(MISCREG_FPRS));
+        gdbregs.regs[RegFsr] = htobe(context->readMiscReg(MISCREG_FSR));
+        gdbregs.regs[RegFprs] = htobe(context->readMiscReg(MISCREG_FPRS));
         gdbregs.regs[RegY] = htobe(context->readIntReg(NumIntArchRegs + 1));
         gdbregs.regs[RegState] = htobe(
-            context->readMiscRegWithEffect(MISCREG_CWP) |
-            context->readMiscRegWithEffect(MISCREG_PSTATE) << 8 |
-            context->readMiscRegWithEffect(MISCREG_ASI) << 24 |
+            context->readMiscReg(MISCREG_CWP) |
+            context->readMiscReg(MISCREG_PSTATE) << 8 |
+            context->readMiscReg(MISCREG_ASI) << 24 |
             context->readIntReg(NumIntArchRegs + 2) << 32);
     }
 
diff --git a/src/arch/sparc/stacktrace.cc b/src/arch/sparc/stacktrace.cc
index 2eb697bf2..2d7991267 100644
--- a/src/arch/sparc/stacktrace.cc
+++ b/src/arch/sparc/stacktrace.cc
@@ -146,7 +146,7 @@ namespace SparcISA
 #if 0
         tc = _tc;
 
-        bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+        bool usermode = (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
 
         Addr pc = tc->readNextPC();
         bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
@@ -221,22 +221,22 @@ namespace SparcISA
     StackTrace::isEntry(Addr addr)
     {
 #if 0
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp12))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp7))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp11))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp21))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp9))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp2))
             return true;
 #endif
         return false;
diff --git a/src/arch/sparc/syscallreturn.hh b/src/arch/sparc/syscallreturn.hh
index d92b12790..cf13fc3e8 100644
--- a/src/arch/sparc/syscallreturn.hh
+++ b/src/arch/sparc/syscallreturn.hh
@@ -49,13 +49,13 @@ namespace SparcISA
             // no error, clear XCC.C
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
-            //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) & 0xEE);
+            //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
             tc->setIntReg(ReturnValueReg, return_value.value());
         } else {
             // got an error, set XCC.C
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) | 0x11);
-            //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) | 0x11);
+            //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
             tc->setIntReg(ReturnValueReg, -return_value.value());
         }
     }
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 41d55158e..c39969769 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -396,7 +396,7 @@ TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
         bool se, FaultTypes ft, int asi)
 {
     uint64_t sfsr;
-    sfsr = tc->readMiscReg(reg);
+    sfsr = tc->readMiscRegNoEffect(reg);
 
     if (sfsr & 0x1)
         sfsr = 0x3;
@@ -410,7 +410,7 @@ TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
         sfsr |= 1 << 6;
     sfsr |= ft << 7;
     sfsr |= asi << 16;
-    tc->setMiscRegWithEffect(reg, sfsr);
+    tc->setMiscReg(reg, sfsr);
 }
 
 void
@@ -419,7 +419,7 @@ TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
     DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
             va, context, mbits(va, 63,13) | mbits(context,12,0));
 
-    tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
+    tc->setMiscReg(reg, mbits(va, 63,13) | mbits(context,12,0));
 }
 
 void
@@ -444,7 +444,7 @@ DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
     DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
             a, (int)write, ct, ft, asi);
     TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
-    tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
+    tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a);
 }
 
 void
@@ -458,7 +458,7 @@ DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 Fault
 ITB::translate(RequestPtr &req, ThreadContext *tc)
 {
-    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
+    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 
     Addr vaddr = req->getVaddr();
     TlbEntry *e;
@@ -572,7 +572,7 @@ Fault
 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 {
     /* @todo this could really use some profiling and fixing to make it faster! */
-    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
+    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
     Addr vaddr = req->getVaddr();
     Addr size = req->getSize();
     ASI asi;
@@ -864,90 +864,90 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
     switch (asi) {
       case ASI_LSU_CONTROL_REG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
         break;
       case ASI_MMU:
         switch (va) {
           case 0x8:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
             break;
           case 0x10:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
             break;
           default:
             goto doMmuReadError;
         }
         break;
       case ASI_QUEUE:
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
+        pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
                     (va >> 4) - 0x3c));
         break;
       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
         break;
       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
         break;
       case ASI_DMMU_CTXT_ZERO_CONFIG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
         break;
       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
         break;
       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
         break;
       case ASI_IMMU_CTXT_ZERO_CONFIG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
         break;
       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
         break;
       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
         break;
       case ASI_DMMU_CTXT_NONZERO_CONFIG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
         break;
       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
         break;
       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
         break;
       case ASI_IMMU_CTXT_NONZERO_CONFIG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
         break;
       case ASI_SPARC_ERROR_STATUS_REG:
         pkt->set((uint64_t)0);
         break;
       case ASI_HYP_SCRATCHPAD:
       case ASI_SCRATCHPAD:
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
+        pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
         break;
       case ASI_IMMU:
         switch (va) {
           case 0x0:
-            temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+            temp = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS);
             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
             break;
           case 0x18:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_SFSR));
             break;
           case 0x30:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
             break;
           default:
             goto doMmuReadError;
@@ -956,20 +956,20 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
       case ASI_DMMU:
         switch (va) {
           case 0x0:
-            temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
+            temp = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS);
             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
             break;
           case 0x18:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFSR));
             break;
           case 0x20:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFAR));
             break;
           case 0x30:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
             break;
           case 0x80:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
             break;
           default:
                 goto doMmuReadError;
@@ -977,35 +977,35 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_DMMU_TSB_PS0_PTR_REG:
         pkt->set(MakeTsbPtr(Ps0,
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
+            tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS),
+            tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0),
+            tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
+            tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0),
+            tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)));
         break;
       case ASI_DMMU_TSB_PS1_PTR_REG:
         pkt->set(MakeTsbPtr(Ps1,
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
+                tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS),
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)));
         break;
       case ASI_IMMU_TSB_PS0_PTR_REG:
           pkt->set(MakeTsbPtr(Ps0,
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
+                tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)));
         break;
       case ASI_IMMU_TSB_PS1_PTR_REG:
           pkt->set(MakeTsbPtr(Ps1,
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
+                tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)));
         break;
       case ASI_SWVR_INTR_RECEIVE:
         pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
@@ -1048,15 +1048,15 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
     switch (asi) {
       case ASI_LSU_CONTROL_REG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
+        tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
         break;
       case ASI_MMU:
         switch (va) {
           case 0x8:
-            tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
+            tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
             break;
           case 0x10:
-            tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
+            tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
             break;
           default:
             goto doMmuWriteError;
@@ -1064,56 +1064,56 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_QUEUE:
         assert(mbits(data,13,6) == data);
-        tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
+        tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
                     (va >> 4) - 0x3c, data);
         break;
       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
         break;
       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
         break;
       case ASI_DMMU_CTXT_ZERO_CONFIG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG, data);
         break;
       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
         break;
       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
         break;
       case ASI_IMMU_CTXT_ZERO_CONFIG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG, data);
         break;
       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
         break;
       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
         break;
       case ASI_DMMU_CTXT_NONZERO_CONFIG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG, data);
         break;
       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
         break;
       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
         break;
       case ASI_IMMU_CTXT_NONZERO_CONFIG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG, data);
         break;
       case ASI_SPARC_ERROR_EN_REG:
       case ASI_SPARC_ERROR_STATUS_REG:
@@ -1121,16 +1121,16 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_HYP_SCRATCHPAD:
       case ASI_SCRATCHPAD:
-        tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
+        tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
         break;
       case ASI_IMMU:
         switch (va) {
           case 0x18:
-            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
+            tc->setMiscReg(MISCREG_MMU_ITLB_SFSR, data);
             break;
           case 0x30:
             sext<59>(bits(data, 59,0));
-            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
+            tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, data);
             break;
           default:
             goto doMmuWriteError;
@@ -1140,10 +1140,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         entry_insert = bits(va, 8,3);
       case ASI_ITLB_DATA_IN_REG:
         assert(entry_insert != -1 || mbits(va,10,9) == va);
-        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+        ta_insert = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS);
         va_insert = mbits(ta_insert, 63,13);
         ct_insert = mbits(ta_insert, 12,0);
-        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
         real_insert = bits(va, 9,9);
         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
                 PageTableEntry::sun4u);
@@ -1154,10 +1154,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         entry_insert = bits(va, 8,3);
       case ASI_DTLB_DATA_IN_REG:
         assert(entry_insert != -1 || mbits(va,10,9) == va);
-        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
+        ta_insert = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS);
         va_insert = mbits(ta_insert, 63,13);
         ct_insert = mbits(ta_insert, 12,0);
-        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
         real_insert = bits(va, 9,9);
         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
                 PageTableEntry::sun4u);
@@ -1166,10 +1166,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
       case ASI_IMMU_DEMAP:
         ignore = false;
         ctx_id = -1;
-        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
         switch (bits(va,5,4)) {
           case 0:
-            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
+            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
             break;
           case 1:
             ignore = true;
@@ -1201,14 +1201,14 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
       case ASI_DMMU:
         switch (va) {
           case 0x18:
-            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
+            tc->setMiscReg(MISCREG_MMU_DTLB_SFSR, data);
             break;
           case 0x30:
             sext<59>(bits(data, 59,0));
-            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
+            tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, data);
             break;
           case 0x80:
-            tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
+            tc->setMiscReg(MISCREG_MMU_PART_ID, data);
             break;
           default:
             goto doMmuWriteError;
@@ -1217,13 +1217,13 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
       case ASI_DMMU_DEMAP:
         ignore = false;
         ctx_id = -1;
-        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
         switch (bits(va,5,4)) {
           case 0:
-            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
+            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
             break;
           case 1:
-            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
+            ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
             break;
           case 3:
             ctx_id = 0;
@@ -1274,25 +1274,25 @@ DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 {
     uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
     ptrs[0] = MakeTsbPtr(Ps0, tag_access,
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
     ptrs[1] = MakeTsbPtr(Ps1, tag_access,
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
     ptrs[2] = MakeTsbPtr(Ps0, tag_access,
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
     ptrs[3] = MakeTsbPtr(Ps1, tag_access,
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
 }
 
 
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 5b13cd041..7a16dc352 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -66,18 +66,18 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
     switch (miscReg) {
         /* Full system only ASRs */
       case MISCREG_SOFTINT:
-        setReg(miscReg, val);;
+        setRegNoEffect(miscReg, val);;
         checkSoftInt(tc);
         break;
       case MISCREG_SOFTINT_CLR:
-        return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
+        return setReg(MISCREG_SOFTINT, ~val & softint, tc);
       case MISCREG_SOFTINT_SET:
-        return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
+        return setReg(MISCREG_SOFTINT, val | softint, tc);
 
       case MISCREG_TICK_CMPR:
         if (tickCompare == NULL)
             tickCompare = new TickCompareEvent(this, tc);
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
             tickCompare->deschedule();
         time = (tick_cmpr & mask(63)) - (tick & mask(63));
@@ -92,7 +92,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
       case MISCREG_STICK_CMPR:
         if (sTickCompare == NULL)
             sTickCompare = new STickCompareEvent(this, tc);
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
             sTickCompare->deschedule();
         time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
@@ -106,10 +106,10 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
 
       case MISCREG_PSTATE:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
 
       case MISCREG_PIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         checkSoftInt(tc);
         break;
 
@@ -117,7 +117,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         panic("Shouldn't be writing HVER\n");
 
       case MISCREG_HINTP:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if (hintp)
             tc->getCpuPtr()->post_interrupt(IT_HINTP,0);
         else
@@ -126,12 +126,12 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
 
       case MISCREG_HTBA:
         // clear lower 7 bits on writes.
-        setReg(miscReg, val & ULL(~0x7FFF));
+        setRegNoEffect(miscReg, val & ULL(~0x7FFF));
         break;
 
       case MISCREG_QUEUE_CPU_MONDO_HEAD:
       case MISCREG_QUEUE_CPU_MONDO_TAIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if (cpu_mondo_head != cpu_mondo_tail)
             tc->getCpuPtr()->post_interrupt(IT_CPU_MONDO,0);
         else
@@ -139,7 +139,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
       case MISCREG_QUEUE_DEV_MONDO_HEAD:
       case MISCREG_QUEUE_DEV_MONDO_TAIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if (dev_mondo_head != dev_mondo_tail)
             tc->getCpuPtr()->post_interrupt(IT_DEV_MONDO,0);
         else
@@ -147,7 +147,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
       case MISCREG_QUEUE_RES_ERROR_HEAD:
       case MISCREG_QUEUE_RES_ERROR_TAIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if (res_error_head != res_error_tail)
             tc->getCpuPtr()->post_interrupt(IT_RES_ERROR,0);
         else
@@ -155,14 +155,14 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
       case MISCREG_QUEUE_NRES_ERROR_HEAD:
       case MISCREG_QUEUE_NRES_ERROR_TAIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         // This one doesn't have an interrupt to report to the guest OS
         break;
 
       case MISCREG_HSTICK_CMPR:
         if (hSTickCompare == NULL)
             hSTickCompare = new HSTickCompareEvent(this, tc);
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
             hSTickCompare->deschedule();
         time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
@@ -177,7 +177,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
 
       case MISCREG_HPSTATE:
         // T1000 spec says impl. dependent val must always be 1
-        setReg(miscReg, val | HPSTATE::id);
+        setRegNoEffect(miscReg, val | HPSTATE::id);
 #if FULL_SYSTEM
         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
             tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
@@ -187,7 +187,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
       case MISCREG_HTSTATE:
       case MISCREG_STRAND_STS_REG:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         break;
 
       default:
@@ -217,10 +217,10 @@ MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
       case MISCREG_HTSTATE:
       case MISCREG_STRAND_STS_REG:
       case MISCREG_HSTICK_CMPR:
-        return readReg(miscReg) ;
+        return readRegNoEffect(miscReg) ;
 
       case MISCREG_HTBA:
-        return readReg(miscReg) & ULL(~0x7FFF);
+        return readRegNoEffect(miscReg) & ULL(~0x7FFF);
       case MISCREG_HVER:
         return NWindows | MaxTL << 8 | MaxGL << 16;
 
@@ -259,8 +259,8 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
     if (ticks == 0) {
         DPRINTF(Timer, "STick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
-        if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
-            setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
+        if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
+            setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
         }
     } else
         sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
@@ -280,8 +280,8 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
     if (ticks == 0) {
         DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
-        if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
-            setRegWithEffect(MISCREG_HINTP, 1, tc);
+        if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
+            setReg(MISCREG_HINTP, 1, tc);
         }
         // Need to do something to cause interrupt to happen here !!! @todo
     } else
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 3c8bdcd01..64b91695e 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -44,8 +44,8 @@ namespace SparcISA
     static inline bool
     inUserMode(ThreadContext *tc)
     {
-        return !(tc->readMiscReg(MISCREG_PSTATE & (1 << 2)) ||
-                tc->readMiscReg(MISCREG_HPSTATE & (1 << 2)));
+        return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
+                tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
     }
 
     inline ExtMachInst
@@ -56,7 +56,7 @@ namespace SparcISA
         //slightly redundant, but it removes the need to put a condition
         //into all the execute functions
         if(inst & (1 << 13))
-            emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
+            emi |= (static_cast<ExtMachInst>(xc->readMiscRegNoEffect(MISCREG_ASI))
                     << (sizeof(MachInst) * 8));
         else
             emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
index cb545185a..9a93950d2 100644
--- a/src/arch/sparc/vtophys.cc
+++ b/src/arch/sparc/vtophys.cc
@@ -66,7 +66,7 @@ namespace SparcISA
         // 4. We are not priv, use ctxN0* tsbs to find the page
         // For all accesses we check the tlbs first since it's possible that
         // long standing pages (e.g. locked kernel mappings) won't be in the tsb
-        uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
+        uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 
         bool hpriv = bits(tlbdata,0,0);
         //bool priv = bits(tlbdata,2,2);
diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc
index bfd3ded5d..287655a97 100644
--- a/src/arch/x86/miscregfile.cc
+++ b/src/arch/x86/miscregfile.cc
@@ -103,22 +103,22 @@ void MiscRegFile::clear()
     panic("No misc registers in x86 yet!\n");
 }
 
-MiscReg MiscRegFile::readReg(int miscReg)
+MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 {
     panic("No misc registers in x86 yet!\n");
 }
 
-MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
+MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 {
     panic("No misc registers in x86 yet!\n");
 }
 
-void MiscRegFile::setReg(int miscReg, const MiscReg &val)
+void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 {
     panic("No misc registers in x86 yet!\n");
 }
 
-void MiscRegFile::setRegWithEffect(int miscReg,
+void MiscRegFile::setReg(int miscReg,
         const MiscReg &val, ThreadContext * tc)
 {
     panic("No misc registers in x86 yet!\n");
diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh
index be04cd528..10acb97a4 100644
--- a/src/arch/x86/miscregfile.hh
+++ b/src/arch/x86/miscregfile.hh
@@ -113,13 +113,13 @@ namespace X86ISA
             clear();
         }
 
-        MiscReg readReg(int miscReg);
+        MiscReg readRegNoEffect(int miscReg);
 
-        MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
+        MiscReg readReg(int miscReg, ThreadContext *tc);
 
-        void setReg(int miscReg, const MiscReg &val);
+        void setRegNoEffect(int miscReg, const MiscReg &val);
 
-        void setRegWithEffect(int miscReg,
+        void setReg(int miscReg,
                 const MiscReg &val, ThreadContext *tc);
 
         void serialize(std::ostream & os);
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 506913a35..568eb1d94 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -130,25 +130,25 @@ void RegFile::clear()
     miscRegFile.clear();
 }
 
-MiscReg RegFile::readMiscReg(int miscReg)
+MiscReg RegFile::readMiscRegNoEffect(int miscReg)
 {
-    return miscRegFile.readReg(miscReg);
+    return miscRegFile.readRegNoEffect(miscReg);
 }
 
-MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
+MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
 {
-    return miscRegFile.readRegWithEffect(miscReg, tc);
+    return miscRegFile.readReg(miscReg, tc);
 }
 
-void RegFile::setMiscReg(int miscReg, const MiscReg &val)
+void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
 {
-    miscRegFile.setReg(miscReg, val);
+    miscRegFile.setRegNoEffect(miscReg, val);
 }
 
-void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
+void RegFile::setMiscReg(int miscReg, const MiscReg &val,
         ThreadContext * tc)
 {
-    miscRegFile.setRegWithEffect(miscReg, val, tc);
+    miscRegFile.setReg(miscReg, val, tc);
 }
 
 FloatReg RegFile::readFloatReg(int floatReg, int width)
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index 41ebcd8de..d4425b04c 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -98,13 +98,13 @@ namespace X86ISA
 
         int FlattenIntIndex(int reg);
 
-        MiscReg readMiscReg(int miscReg);
+        MiscReg readMiscRegNoEffect(int miscReg);
 
-        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
 
-        void setMiscReg(int miscReg, const MiscReg &val);
+        void setMiscRegNoEffect(int miscReg, const MiscReg &val);
 
-        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscReg(int miscReg, const MiscReg &val,
                 ThreadContext * tc);
 
         int instAsid()
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3e08193ee..7b3628986 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -298,27 +298,27 @@ class CheckerCPU : public BaseCPU
         thread->setNextPC(val);
     }
 
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return thread->readMiscReg(misc_reg);
+        return thread->readMiscRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg)
     {
-        return thread->readMiscRegWithEffect(misc_reg);
+        return thread->readMiscReg(misc_reg);
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     {
         result.integer = val;
         miscRegIdxs.push(misc_reg);
-        return thread->setMiscReg(misc_reg, val);
+        return thread->setMiscRegNoEffect(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         miscRegIdxs.push(misc_reg);
-        return thread->setMiscRegWithEffect(misc_reg, val);
+        return thread->setMiscReg(misc_reg, val);
     }
 
     void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 56e13dd1e..f3f8a0bb3 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -386,13 +386,13 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
         int misc_reg_idx = miscRegIdxs.front();
         miscRegIdxs.pop();
 
-        if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
-            thread->readMiscReg(misc_reg_idx)) {
+        if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
+            thread->readMiscRegNoEffect(misc_reg_idx)) {
             warn("%lli: Misc reg idx %i (side effect) does not match! "
                  "Inst: %#x, checker: %#x",
                  curTick, misc_reg_idx,
-                 inst->tcBase()->readMiscReg(misc_reg_idx),
-                 thread->readMiscReg(misc_reg_idx));
+                 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
+                 thread->readMiscRegNoEffect(misc_reg_idx));
             handleError(inst);
         }
     }
@@ -432,7 +432,7 @@ Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
     } else if (idx < TheISA::Fpcr_DepTag) {
         thread->setFloatRegBits(idx, inst->readIntResult());
     } else {
-        thread->setMiscReg(idx, inst->readIntResult());
+        thread->setMiscRegNoEffect(idx, inst->readIntResult());
     }
 }
 
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index cf36d8392..3b4d21e13 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -248,11 +248,17 @@ class CheckerThreadContext : public ThreadContext
         checkerCPU->recordNextPCChange(val);
     }
 
+    MiscReg readMiscRegNoEffect(int misc_reg)
+    { return actualTC->readMiscRegNoEffect(misc_reg); }
+
     MiscReg readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
-    { return actualTC->readMiscRegWithEffect(misc_reg); }
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+    {
+        checkerTC->setMiscRegNoEffect(misc_reg, val);
+        actualTC->setMiscRegNoEffect(misc_reg, val);
+    }
 
     void setMiscReg(int misc_reg, const MiscReg &val)
     {
@@ -260,12 +266,6 @@ class CheckerThreadContext : public ThreadContext
         actualTC->setMiscReg(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
-    {
-        checkerTC->setMiscRegWithEffect(misc_reg, val);
-        actualTC->setMiscRegWithEffect(misc_reg, val);
-    }
-
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }
 
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index edccd747f..2b9fe4bcf 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -100,18 +100,18 @@ class ExecContext {
     void setNextNPC(uint64_t val);
 
     /** Reads a miscellaneous register. */
-    MiscReg readMiscReg(int misc_reg);
+    MiscReg readMiscRegNoEffect(int misc_reg);
 
     /** Reads a miscellaneous register, handling any architectural
      * side effects due to reading that register. */
-    MiscReg readMiscRegWithEffect(int misc_reg);
+    MiscReg readMiscReg(int misc_reg);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const MiscReg &val);
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 
     /** Sets a miscellaneous register, handling any architectural
      * side effects due to writing that register. */
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+    void setMiscReg(int misc_reg, const MiscReg &val);
 
     /** Records the effective address of the instruction.  Only valid
      * for memory ops. */
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index c4d3ae505..54d8c68fa 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -171,14 +171,14 @@ Trace::InstRecord::dump()
             outs << "PC = " << thread->readNextPC();
             outs << " NPC = " << thread->readNextNPC();
             newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
-            //newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
+            //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_CCR);
             if(newVal != ccr)
             {
                 outs << " CCR = " << newVal;
                 ccr = newVal;
             }
             newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1);
-            //newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
+            //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_Y);
             if(newVal != y)
             {
                 outs << " Y = " << newVal;
@@ -387,30 +387,30 @@ Trace::InstRecord::dump()
                             diffFpRegs = true;
                         }
                     }
-                            uint64_t oldTl = thread->readMiscReg(MISCREG_TL);
+                            uint64_t oldTl = thread->readMiscRegNoEffect(MISCREG_TL);
                     if (oldTl != shared_data->tl)
                         diffTl = true;
                     for (int i = 1; i <= MaxTL; i++) {
-                        thread->setMiscReg(MISCREG_TL, i);
-                        if (thread->readMiscReg(MISCREG_TPC) !=
+                        thread->setMiscRegNoEffect(MISCREG_TL, i);
+                        if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
                                 shared_data->tpc[i-1])
                             diffTpc = true;
-                        if (thread->readMiscReg(MISCREG_TNPC) !=
+                        if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
                                 shared_data->tnpc[i-1])
                             diffTnpc = true;
-                        if (thread->readMiscReg(MISCREG_TSTATE) !=
+                        if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
                                 shared_data->tstate[i-1])
                             diffTstate = true;
-                        if (thread->readMiscReg(MISCREG_TT) !=
+                        if (thread->readMiscRegNoEffect(MISCREG_TT) !=
                                 shared_data->tt[i-1])
                             diffTt = true;
-                        if (thread->readMiscReg(MISCREG_HTSTATE) !=
+                        if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
                                 shared_data->htstate[i-1])
                             diffHtstate = true;
                     }
-                    thread->setMiscReg(MISCREG_TL, oldTl);
+                    thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
 
-                    if(shared_data->tba != thread->readMiscReg(MISCREG_TBA))
+                    if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
                         diffTba = true;
                     //When the hpstate register is read by an instruction,
                     //legion has bit 11 set. When it's in storage, it doesn't.
@@ -418,50 +418,50 @@ Trace::InstRecord::dump()
                     //of the registers like that, the bit is always set to 1 and
                     //we just don't compare it. It's not supposed to matter
                     //anyway.
-                    if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE))
+                    if((shared_data->hpstate | (1 << 11)) != thread->readMiscRegNoEffect(MISCREG_HPSTATE))
                         diffHpstate = true;
-                    if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA))
+                    if(shared_data->htba != thread->readMiscRegNoEffect(MISCREG_HTBA))
                         diffHtba = true;
-                    if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE))
+                    if(shared_data->pstate != thread->readMiscRegNoEffect(MISCREG_PSTATE))
                         diffPstate = true;
-                    //if(shared_data->y != thread->readMiscReg(MISCREG_Y))
+                    //if(shared_data->y != thread->readMiscRegNoEffect(MISCREG_Y))
                     if(shared_data->y !=
                             thread->readIntReg(NumIntArchRegs + 1))
                         diffY = true;
-                    if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) {
+                    if(shared_data->fsr != thread->readMiscRegNoEffect(MISCREG_FSR)) {
                         diffFsr = true;
                         if (mbits(shared_data->fsr, 63,10) ==
-                                mbits(thread->readMiscReg(MISCREG_FSR), 63,10)) {
-                            thread->setMiscReg(MISCREG_FSR, shared_data->fsr);
+                                mbits(thread->readMiscRegNoEffect(MISCREG_FSR), 63,10)) {
+                            thread->setMiscRegNoEffect(MISCREG_FSR, shared_data->fsr);
                             diffFsr = false;
                         }
                     }
-                    //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
+                    //if(shared_data->ccr != thread->readMiscRegNoEffect(MISCREG_CCR))
                     if(shared_data->ccr !=
                             thread->readIntReg(NumIntArchRegs + 2))
                         diffCcr = true;
-                    if(shared_data->gl != thread->readMiscReg(MISCREG_GL))
+                    if(shared_data->gl != thread->readMiscRegNoEffect(MISCREG_GL))
                         diffGl = true;
-                    if(shared_data->asi != thread->readMiscReg(MISCREG_ASI))
+                    if(shared_data->asi != thread->readMiscRegNoEffect(MISCREG_ASI))
                         diffAsi = true;
-                    if(shared_data->pil != thread->readMiscReg(MISCREG_PIL))
+                    if(shared_data->pil != thread->readMiscRegNoEffect(MISCREG_PIL))
                         diffPil = true;
-                    if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP))
+                    if(shared_data->cwp != thread->readMiscRegNoEffect(MISCREG_CWP))
                         diffCwp = true;
-                    //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
+                    //if(shared_data->cansave != thread->readMiscRegNoEffect(MISCREG_CANSAVE))
                     if(shared_data->cansave !=
                             thread->readIntReg(NumIntArchRegs + 3))
                         diffCansave = true;
                     //if(shared_data->canrestore !=
-                    //	    thread->readMiscReg(MISCREG_CANRESTORE))
+                    //	    thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
                     if(shared_data->canrestore !=
                             thread->readIntReg(NumIntArchRegs + 4))
                         diffCanrestore = true;
-                    //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
+                    //if(shared_data->otherwin != thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
                     if(shared_data->otherwin !=
                             thread->readIntReg(NumIntArchRegs + 6))
                         diffOtherwin = true;
-                    //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
+                    //if(shared_data->cleanwin != thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
                     if(shared_data->cleanwin !=
                             thread->readIntReg(NumIntArchRegs + 5))
                         diffCleanwin = true;
@@ -569,78 +569,78 @@ Trace::InstRecord::dump()
                         printSectionHeader(outs, "General State");
                         printColumnLabels(outs);
                         printRegPair(outs, "HPstate",
-                                thread->readMiscReg(MISCREG_HPSTATE),
+                                thread->readMiscRegNoEffect(MISCREG_HPSTATE),
                                 shared_data->hpstate | (1 << 11));
                         printRegPair(outs, "Htba",
-                                thread->readMiscReg(MISCREG_HTBA),
+                                thread->readMiscRegNoEffect(MISCREG_HTBA),
                                 shared_data->htba);
                         printRegPair(outs, "Pstate",
-                                thread->readMiscReg(MISCREG_PSTATE),
+                                thread->readMiscRegNoEffect(MISCREG_PSTATE),
                                 shared_data->pstate);
                         printRegPair(outs, "Y",
-                                //thread->readMiscReg(MISCREG_Y),
+                                //thread->readMiscRegNoEffect(MISCREG_Y),
                                 thread->readIntReg(NumIntArchRegs + 1),
                                 shared_data->y);
                         printRegPair(outs, "FSR",
-                                thread->readMiscReg(MISCREG_FSR),
+                                thread->readMiscRegNoEffect(MISCREG_FSR),
                                 shared_data->fsr);
                         printRegPair(outs, "Ccr",
-                                //thread->readMiscReg(MISCREG_CCR),
+                                //thread->readMiscRegNoEffect(MISCREG_CCR),
                                 thread->readIntReg(NumIntArchRegs + 2),
                                 shared_data->ccr);
                         printRegPair(outs, "Tl",
-                                thread->readMiscReg(MISCREG_TL),
+                                thread->readMiscRegNoEffect(MISCREG_TL),
                                 shared_data->tl);
                         printRegPair(outs, "Gl",
-                                thread->readMiscReg(MISCREG_GL),
+                                thread->readMiscRegNoEffect(MISCREG_GL),
                                 shared_data->gl);
                         printRegPair(outs, "Asi",
-                                thread->readMiscReg(MISCREG_ASI),
+                                thread->readMiscRegNoEffect(MISCREG_ASI),
                                 shared_data->asi);
                         printRegPair(outs, "Pil",
-                                thread->readMiscReg(MISCREG_PIL),
+                                thread->readMiscRegNoEffect(MISCREG_PIL),
                                 shared_data->pil);
                         printRegPair(outs, "Cwp",
-                                thread->readMiscReg(MISCREG_CWP),
+                                thread->readMiscRegNoEffect(MISCREG_CWP),
                                 shared_data->cwp);
                         printRegPair(outs, "Cansave",
-                                //thread->readMiscReg(MISCREG_CANSAVE),
+                                //thread->readMiscRegNoEffect(MISCREG_CANSAVE),
                                 thread->readIntReg(NumIntArchRegs + 3),
                                 shared_data->cansave);
                         printRegPair(outs, "Canrestore",
-                                //thread->readMiscReg(MISCREG_CANRESTORE),
+                                //thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
                                 thread->readIntReg(NumIntArchRegs + 4),
                                 shared_data->canrestore);
                         printRegPair(outs, "Otherwin",
-                                //thread->readMiscReg(MISCREG_OTHERWIN),
+                                //thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
                                 thread->readIntReg(NumIntArchRegs + 6),
                                 shared_data->otherwin);
                         printRegPair(outs, "Cleanwin",
-                                //thread->readMiscReg(MISCREG_CLEANWIN),
+                                //thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
                                 thread->readIntReg(NumIntArchRegs + 5),
                                 shared_data->cleanwin);
                         outs << endl;
                         for (int i = 1; i <= MaxTL; i++) {
                             printLevelHeader(outs, i);
                             printColumnLabels(outs);
-                            thread->setMiscReg(MISCREG_TL, i);
+                            thread->setMiscRegNoEffect(MISCREG_TL, i);
                             printRegPair(outs, "Tpc",
-                                    thread->readMiscReg(MISCREG_TPC),
+                                    thread->readMiscRegNoEffect(MISCREG_TPC),
                                     shared_data->tpc[i-1]);
                             printRegPair(outs, "Tnpc",
-                                    thread->readMiscReg(MISCREG_TNPC),
+                                    thread->readMiscRegNoEffect(MISCREG_TNPC),
                                     shared_data->tnpc[i-1]);
                             printRegPair(outs, "Tstate",
-                                    thread->readMiscReg(MISCREG_TSTATE),
+                                    thread->readMiscRegNoEffect(MISCREG_TSTATE),
                                     shared_data->tstate[i-1]);
                             printRegPair(outs, "Tt",
-                                    thread->readMiscReg(MISCREG_TT),
+                                    thread->readMiscRegNoEffect(MISCREG_TT),
                                     shared_data->tt[i-1]);
                             printRegPair(outs, "Htstate",
-                                    thread->readMiscReg(MISCREG_HTSTATE),
+                                    thread->readMiscRegNoEffect(MISCREG_HTSTATE),
                                     shared_data->htstate[i-1]);
                         }
-                        thread->setMiscReg(MISCREG_TL, oldTl);
+                        thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
                         outs << endl;
 
                         printSectionHeader(outs, "General Purpose Registers");
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 4a2086296..676893098 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -106,21 +106,21 @@ class AlphaO3CPU : public FullO3CPU<Impl>
 
 #endif
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
             unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
             unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 41f149963..b91972704 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -154,32 +154,32 @@ AlphaO3CPU<Impl>::regStats()
 
 template <class Impl>
 TheISA::MiscReg
-AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
+AlphaO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscReg(misc_reg, tid);
+    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
 }
 
 template <class Impl>
 TheISA::MiscReg
-AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
+AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
+    return this->regFile.readMiscReg(misc_reg, tid);
 }
 
 template <class Impl>
 void
-AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val,
+AlphaO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
         unsigned tid)
 {
-    this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
 }
 
 template <class Impl>
 void
-AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
+AlphaO3CPU<Impl>::setMiscReg(int misc_reg,
         const TheISA::MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
@@ -209,7 +209,7 @@ Fault
 AlphaO3CPU<Impl>::hwrei(unsigned tid)
 {
     // Need to clear the lock flag upon returning from an interrupt.
-    this->setMiscReg(AlphaISA::MISCREG_LOCKFLAG, false, tid);
+    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
 
     this->thread[tid]->kernelStats->hwrei();
 
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 603a1b52d..6c27e890a 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -95,39 +95,39 @@ class AlphaDynInst : public BaseDynInst<Impl>
 
   public:
     /** Reads a miscellaneous register. */
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
+        return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
     }
 
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
+        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
+        return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
     }
 
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(misc_reg, val,
+        return this->cpu->setMiscReg(misc_reg, val,
                                                this->threadNumber);
     }
 
     /** Reads a miscellaneous register. */
     TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscReg(
+        return this->cpu->readMiscRegNoEffect(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -137,7 +137,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
      */
     TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscRegWithEffect(
+        return this->cpu->readMiscReg(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -146,7 +146,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(
+        return this->cpu->setMiscRegNoEffect(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }
@@ -157,7 +157,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     void setMiscRegOperandWithEffect(const StaticInst *si, int idx,
                                      const MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(
+        return this->cpu->setMiscReg(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }
diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index 50cdec408..fdce1ade5 100644
--- a/src/cpu/o3/alpha/dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -118,7 +118,7 @@ AlphaDynInst<Impl>::hwrei()
         return new AlphaISA::UnimplementedOpcodeFault;
 
     // Set the next PC based on the value of the EXC_ADDR IPR.
-    this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
+    this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
                                            this->threadNumber));
 
     // Tell CPU to clear any state it needs to if a hwrei is taken.
diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh
index 7e6268cdf..0361c1814 100755
--- a/src/cpu/o3/mips/cpu.hh
+++ b/src/cpu/o3/mips/cpu.hh
@@ -87,20 +87,20 @@ class MipsO3CPU : public FullO3CPU<Impl>
     }
 
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg,
+    void setMiscReg(int misc_reg,
             const TheISA::MiscReg &val, unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh
index e7dbd3aba..317fd748e 100644
--- a/src/cpu/o3/mips/cpu_impl.hh
+++ b/src/cpu/o3/mips/cpu_impl.hh
@@ -135,31 +135,31 @@ MipsO3CPU<Impl>::regStats()
 
 template <class Impl>
 MiscReg
-MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
+MipsO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscReg(misc_reg, tid);
+    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
 }
 
 template <class Impl>
 MiscReg
-MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
+MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
+    return this->regFile.readMiscReg(misc_reg, tid);
 }
 
 template <class Impl>
 void
-MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
+MipsO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
 }
 
 template <class Impl>
 void
-MipsO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
+MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val,
                                        unsigned tid)
 {
-    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index f53530908..366b4bb23 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -93,32 +93,32 @@ class MipsDynInst : public BaseDynInst<Impl>
 
   public:
     /** Reads a miscellaneous register. */
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
+        return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
     }
 
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
+        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     {
         this->instResult.integer = val;
-        this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
+        this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
     }
 
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(misc_reg, val,
+        return this->cpu->setMiscReg(misc_reg, val,
                                                this->threadNumber);
     }
 
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 598af123e..c4f8f3a9f 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -225,26 +225,26 @@ class PhysRegFile
         floatRegFile[reg_idx].q = val;
     }
 
-    MiscReg readMiscReg(int misc_reg, unsigned thread_id)
+    MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id)
     {
-        return miscRegs[thread_id].readReg(misc_reg);
+        return miscRegs[thread_id].readRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
+    MiscReg readMiscReg(int misc_reg, unsigned thread_id)
     {
-        return miscRegs[thread_id].readRegWithEffect(misc_reg,
+        return miscRegs[thread_id].readReg(misc_reg,
                                                      cpu->tcBase(thread_id));
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned thread_id)
     {
-        miscRegs[thread_id].setReg(misc_reg, val);
+        miscRegs[thread_id].setRegNoEffect(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
+    void setMiscReg(int misc_reg, const MiscReg &val,
                                unsigned thread_id)
     {
-        miscRegs[thread_id].setRegWithEffect(misc_reg, val,
+        miscRegs[thread_id].setReg(misc_reg, val,
                                                     cpu->tcBase(thread_id));
     }
 
diff --git a/src/cpu/o3/sparc/cpu.hh b/src/cpu/o3/sparc/cpu.hh
index 08ebd2710..7b932e429 100644
--- a/src/cpu/o3/sparc/cpu.hh
+++ b/src/cpu/o3/sparc/cpu.hh
@@ -106,20 +106,20 @@ class SparcO3CPU : public FullO3CPU<Impl>
 
 #endif
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
             unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index c039a8fec..a425a8a56 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -153,32 +153,32 @@ SparcO3CPU<Impl>::regStats()
 
 template <class Impl>
 TheISA::MiscReg
-SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
+SparcO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscReg(misc_reg, tid);
+    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
 }
 
 template <class Impl>
 TheISA::MiscReg
-SparcO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
+SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
+    return this->regFile.readMiscReg(misc_reg, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscReg(int misc_reg,
+SparcO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
         const SparcISA::MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
+SparcO3CPU<Impl>::setMiscReg(int misc_reg,
         const SparcISA::MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/sparc/dyn_inst.hh b/src/cpu/o3/sparc/dyn_inst.hh
index 4314488b5..bd61b0384 100644
--- a/src/cpu/o3/sparc/dyn_inst.hh
+++ b/src/cpu/o3/sparc/dyn_inst.hh
@@ -77,39 +77,39 @@ class SparcDynInst : public BaseDynInst<Impl>
 
   public:
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg)
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
+        return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
     }
 
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg)
+    TheISA::MiscReg readMiscReg(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
+        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
+        return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
     }
 
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val)
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(misc_reg, val,
+        return this->cpu->setMiscReg(misc_reg, val,
                                                this->threadNumber);
     }
 
     /** Reads a miscellaneous register. */
     TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscReg(
+        return this->cpu->readMiscRegNoEffect(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -119,7 +119,7 @@ class SparcDynInst : public BaseDynInst<Impl>
      */
     TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscRegWithEffect(
+        return this->cpu->readMiscReg(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -129,7 +129,7 @@ class SparcDynInst : public BaseDynInst<Impl>
             int idx, const TheISA::MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(
+        return this->cpu->setMiscRegNoEffect(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }
@@ -140,7 +140,7 @@ class SparcDynInst : public BaseDynInst<Impl>
     void setMiscRegOperandWithEffect(
             const StaticInst *si, int idx, const TheISA::MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(
+        return this->cpu->setMiscReg(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 4987d6eb4..93638673b 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -206,20 +206,20 @@ class O3ThreadContext : public ThreadContext
     virtual void setNextPC(uint64_t val);
 
     /** Reads a miscellaneous register. */
-    virtual MiscReg readMiscReg(int misc_reg)
-    { return cpu->readMiscReg(misc_reg, thread->readTid()); }
+    virtual MiscReg readMiscRegNoEffect(int misc_reg)
+    { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
 
     /** Reads a misc. register, including any side-effects the
      * read might have as defined by the architecture. */
-    virtual MiscReg readMiscRegWithEffect(int misc_reg)
-    { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); }
+    virtual MiscReg readMiscReg(int misc_reg)
+    { return cpu->readMiscReg(misc_reg, thread->readTid()); }
 
     /** Sets a misc. register. */
-    virtual void setMiscReg(int misc_reg, const MiscReg &val);
+    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 
     /** Sets a misc. register, including any side-effects the
      * write might have as defined by the architecture. */
-    virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+    virtual void setMiscReg(int misc_reg, const MiscReg &val);
 
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index af98fa1f5..d2acc6232 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -442,9 +442,9 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
+O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 {
-    cpu->setMiscReg(misc_reg, val, thread->readTid());
+    cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
@@ -454,10 +454,10 @@ O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
+O3ThreadContext<Impl>::setMiscReg(int misc_reg,
                                                 const MiscReg &val)
 {
-    cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid());
+    cpu->setMiscReg(misc_reg, val, thread->readTid());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index baea7a546..2432df55e 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -235,14 +235,14 @@ class OzoneCPU : public BaseCPU
 
       public:
         // ISA stuff:
+        MiscReg readMiscRegNoEffect(int misc_reg);
+
         MiscReg readMiscReg(int misc_reg);
 
-        MiscReg readMiscRegWithEffect(int misc_reg);
+        void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 
         void setMiscReg(int misc_reg, const MiscReg &val);
 
-        void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
-
         unsigned readStCondFailures()
         { return thread->storeCondFailures; }
 
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index a854de8de..4a76ae110 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -1089,24 +1089,24 @@ OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
 
 template <class Impl>
 TheISA::MiscReg
-OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
+OzoneCPU<Impl>::OzoneTC::readMiscRegNoEffect(int misc_reg)
 {
-    return thread->miscRegFile.readReg(misc_reg);
+    return thread->miscRegFile.readRegNoEffect(misc_reg);
 }
 
 template <class Impl>
 TheISA::MiscReg
-OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg)
+OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
 {
-    return thread->miscRegFile.readRegWithEffect(misc_reg, this);
+    return thread->miscRegFile.readReg(misc_reg, this);
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
+OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 {
     // Needs to setup a squash event unless we're in syscall mode
-    thread->miscRegFile.setReg(misc_reg, val);
+    thread->miscRegFile.setRegNoEffect(misc_reg, val);
 
     if (!thread->inSyscall) {
         cpu->squashFromTC();
@@ -1115,10 +1115,10 @@ OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
 {
     // Needs to setup a squash event unless we're in syscall mode
-    thread->miscRegFile.setRegWithEffect(misc_reg, val, this);
+    thread->miscRegFile.setReg(misc_reg, val, this);
 
     if (!thread->inSyscall) {
         cpu->squashFromTC();
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 88f96b14b..e138cbe13 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -231,14 +231,14 @@ class OzoneDynInst : public BaseDynInst<Impl>
 
   public:
     // ISA stuff
+    MiscReg readMiscRegNoEffect(int misc_reg);
+
     MiscReg readMiscReg(int misc_reg);
 
-    MiscReg readMiscRegWithEffect(int misc_reg);
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 
     void setMiscReg(int misc_reg, const MiscReg &val);
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
-
 #if FULL_SYSTEM
     Fault hwrei();
     void trap(Fault fault);
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 05a66d77a..8519917f5 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -219,31 +219,31 @@ OzoneDynInst<Impl>::clearMemDependents()
 
 template <class Impl>
 TheISA::MiscReg
-OzoneDynInst<Impl>::readMiscReg(int misc_reg)
+OzoneDynInst<Impl>::readMiscRegNoEffect(int misc_reg)
 {
-    return this->thread->readMiscReg(misc_reg);
+    return this->thread->readMiscRegNoEffect(misc_reg);
 }
 
 template <class Impl>
 TheISA::MiscReg
-OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg)
+OzoneDynInst<Impl>::readMiscReg(int misc_reg)
 {
-    return this->thread->readMiscRegWithEffect(misc_reg);
+    return this->thread->readMiscReg(misc_reg);
 }
 
 template <class Impl>
 void
-OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
+OzoneDynInst<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 {
     this->setIntResult(val);
-    this->thread->setMiscReg(misc_reg, val);
+    this->thread->setMiscRegNoEffect(misc_reg, val);
 }
 
 template <class Impl>
 void
-OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 {
-    this->thread->setMiscRegWithEffect(misc_reg, val);
+    this->thread->setMiscReg(misc_reg, val);
 }
 
 #if FULL_SYSTEM
@@ -255,7 +255,7 @@ OzoneDynInst<Impl>::hwrei()
     if (!(this->readPC() & 0x3))
         return new AlphaISA::UnimplementedOpcodeFault;
 
-    this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
+    this->setNextPC(this->thread->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
 
     this->cpu->hwrei();
 
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 84f935a72..8d7ebb60e 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -89,13 +89,13 @@ InorderBackEnd<Impl>::checkInterrupts()
     int summary = 0;
 
 
-    if (thread->readMiscReg(IPR_ASTRR))
+    if (thread->readMiscRegNoEffect(IPR_ASTRR))
         panic("asynchronous traps not implemented\n");
 
-    if (thread->readMiscReg(IPR_SIRR)) {
+    if (thread->readMiscRegNoEffect(IPR_SIRR)) {
         for (int i = INTLEVEL_SOFTWARE_MIN;
              i < INTLEVEL_SOFTWARE_MAX; i++) {
-            if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+            if (thread->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
                 // See table 4-19 of the 21164 hardware reference
                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                 summary |= (ULL(1) << i);
@@ -116,14 +116,14 @@ InorderBackEnd<Impl>::checkInterrupts()
         }
     }
 
-    if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
+    if (ipl && ipl > thread->readMiscRegNoEffect(IPR_IPLR)) {
         thread->inSyscall = true;
 
-        thread->setMiscReg(IPR_ISR, summary);
-        thread->setMiscReg(IPR_INTID, ipl);
+        thread->setMiscRegNoEffect(IPR_ISR, summary);
+        thread->setMiscRegNoEffect(IPR_INTID, ipl);
         Fault(new InterruptFault)->invoke(xc);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                thread->readMiscReg(IPR_IPLR), ipl, summary);
+                thread->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
 
         // May need to go 1 inst prior
         squashPending = true;
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index a181c93f4..c0a9cad24 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -1193,7 +1193,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
 #if FULL_SYSTEM
     if (thread->profile) {
 //        bool usermode =
-//            (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+//            (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
 //        thread->profilePC = usermode ? 1 : inst->readPC();
         thread->profilePC = inst->readPC();
         ProfileNode *node = thread->profile->consume(thread->getTC(),
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index a71795851..53776e7d9 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -115,24 +115,24 @@ struct OzoneThreadState : public ThreadState {
 
     ThreadContext *getTC() { return tc; }
 
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return miscRegFile.readReg(misc_reg);
+        return miscRegFile.readRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg)
     {
-        return miscRegFile.readRegWithEffect(misc_reg, tc);
+        return miscRegFile.readReg(misc_reg, tc);
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     {
-        miscRegFile.setReg(misc_reg, val);
+        miscRegFile.setRegNoEffect(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
-        miscRegFile.setRegWithEffect(misc_reg, val, tc);
+        miscRegFile.setReg(misc_reg, val, tc);
     }
 
     uint64_t readPC()
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 01c8e8eb7..980ea2f96 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -284,14 +284,19 @@ class BaseSimpleCPU : public BaseCPU
     void setNextPC(uint64_t val) { thread->setNextPC(val); }
     void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
 
+    MiscReg readMiscRegNoEffect(int misc_reg)
+    {
+        return thread->readMiscRegNoEffect(misc_reg);
+    }
+
     MiscReg readMiscReg(int misc_reg)
     {
         return thread->readMiscReg(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     {
-        return thread->readMiscRegWithEffect(misc_reg);
+        return thread->setMiscRegNoEffect(misc_reg, val);
     }
 
     void setMiscReg(int misc_reg, const MiscReg &val)
@@ -299,34 +304,29 @@ class BaseSimpleCPU : public BaseCPU
         return thread->setMiscReg(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
-    {
-        return thread->setMiscRegWithEffect(misc_reg, val);
-    }
-
     MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
-        return thread->readMiscReg(reg_idx);
+        return thread->readMiscRegNoEffect(reg_idx);
     }
 
     MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
-        return thread->readMiscRegWithEffect(reg_idx);
+        return thread->readMiscReg(reg_idx);
     }
 
     void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
-        return thread->setMiscReg(reg_idx, val);
+        return thread->setMiscRegNoEffect(reg_idx, val);
     }
 
     void setMiscRegOperandWithEffect(
             const StaticInst *si, int idx, const MiscReg &val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
-        return thread->setMiscRegWithEffect(reg_idx, val);
+        return thread->setMiscReg(reg_idx, val);
     }
 
     unsigned readStCondFailures() {
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index f2f79c070..824914ad0 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -350,24 +350,24 @@ class SimpleThread : public ThreadState
         regs.setNextNPC(val);
     }
 
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return regs.readMiscReg(misc_reg);
+        return regs.readMiscRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg)
     {
-        return regs.readMiscRegWithEffect(misc_reg, tc);
+        return regs.readMiscReg(misc_reg, tc);
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     {
-        return regs.setMiscReg(misc_reg, val);
+        return regs.setMiscRegNoEffect(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return regs.setMiscRegWithEffect(misc_reg, val, tc);
+        return regs.setMiscReg(misc_reg, val, tc);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index a24dc49da..05c409c95 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -226,14 +226,14 @@ class ThreadContext
 
     virtual void setNextNPC(uint64_t val) = 0;
 
+    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
+
     virtual MiscReg readMiscReg(int misc_reg) = 0;
 
-    virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
+    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
 
     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 
-    virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
-
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
     virtual unsigned readStCondFailures() = 0;
@@ -412,18 +412,18 @@ class ProxyThreadContext : public ThreadContext
 
     void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
 
+    MiscReg readMiscRegNoEffect(int misc_reg)
+    { return actualTC->readMiscRegNoEffect(misc_reg); }
+
     MiscReg readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
-    { return actualTC->readMiscRegWithEffect(misc_reg); }
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+    { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 
     void setMiscReg(int misc_reg, const MiscReg &val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
-    { return actualTC->setMiscRegWithEffect(misc_reg, val); }
-
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }
 
diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh
index 6645aa865..b94276035 100644
--- a/src/kern/tru64/tru64.hh
+++ b/src/kern/tru64/tru64.hh
@@ -511,7 +511,7 @@ class Tru64 : public OperatingSystem
             tc->setFloatRegBits(i, htog(sc->sc_fpregs[i]));
         }
 
-        tc->setMiscReg(AlphaISA::MISCREG_FPCR, htog(sc->sc_fpcr));
+        tc->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR, htog(sc->sc_fpcr));
 
         return 0;
     }
@@ -653,7 +653,7 @@ class Tru64 : public OperatingSystem
             ssp->nxm_sysevent = htog(0);
 
             if (i == 0) {
-                uint64_t uniq = tc->readMiscReg(AlphaISA::MISCREG_UNIQ);
+                uint64_t uniq = tc->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ);
                 ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset));
                 ssp->nxm_u.nxm_active = htog(uniq | 1);
             }
@@ -693,7 +693,7 @@ class Tru64 : public OperatingSystem
         tc->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0));
         tc->setIntReg(27/*t12*/, gtoh(attrp->registers.pc));
         tc->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp));
-        tc->setMiscReg(AlphaISA::MISCREG_UNIQ, uniq_val);
+        tc->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ, uniq_val);
 
         tc->setPC(gtoh(attrp->registers.pc));
         tc->setNextPC(gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst));