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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-14 14:15:30 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-14 14:15:30 -0500
commit6cf9f182f678e4ddf2a2b98a5093a7418353217c (patch)
tree9de2665814818b7ce04cf7b2c85cc907b71a3581 /src
parentac91f90145f824b202d79a9e275fc5cee1071159 (diff)
downloadgem5-6cf9f182f678e4ddf2a2b98a5093a7418353217c.tar.xz
MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which is now split into bus.master and bus.slave. The only non-trivial change is the memtest where the level building now has to be aware of the role of the ports used in the previous level.
Diffstat (limited to 'src')
-rw-r--r--src/dev/arm/RealView.py2
-rwxr-xr-xsrc/dev/mips/Malta.py6
-rw-r--r--src/dev/sparc/T1000.py32
3 files changed, 20 insertions, 20 deletions
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index e42bc4b94..48a7cf316 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -376,7 +376,7 @@ class VExpress_ELT(RealView):
self.elba_kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.config = bus.master
- self.cf_ctrl.dma = bus.port
+ self.cf_ctrl.dma = bus.slave
self.ide.pio = bus.master
self.ide.config = bus.master
self.ide.dma = bus.slave
diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index ddde06687..23a5e5c8f 100755
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -63,6 +63,6 @@ class Malta(Platform):
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
- self.cchip.pio = bus.port
- self.io.pio = bus.port
- self.uart.pio = bus.port
+ self.cchip.pio = bus.master
+ self.io.pio = bus.master
+ self.uart.pio = bus.master
diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index 901304251..aa66a9004 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -109,8 +109,8 @@ class T1000(Platform):
iob = Iob()
# Attach I/O devices that are on chip
def attachOnChipIO(self, bus):
- self.iob.pio = bus.port
- self.htod.pio = bus.port
+ self.iob.pio = bus.master
+ self.htod.pio = bus.master
# Attach I/O devices to specified bus object. Can't do this
@@ -119,17 +119,17 @@ class T1000(Platform):
def attachIO(self, bus):
self.hvuart.terminal = self.hterm
self.puart0.terminal = self.pterm
- self.fake_clk.pio = bus.port
- self.fake_membnks.pio = bus.port
- self.fake_l2_1.pio = bus.port
- self.fake_l2_2.pio = bus.port
- self.fake_l2_3.pio = bus.port
- self.fake_l2_4.pio = bus.port
- self.fake_l2esr_1.pio = bus.port
- self.fake_l2esr_2.pio = bus.port
- self.fake_l2esr_3.pio = bus.port
- self.fake_l2esr_4.pio = bus.port
- self.fake_ssi.pio = bus.port
- self.fake_jbi.pio = bus.port
- self.puart0.pio = bus.port
- self.hvuart.pio = bus.port
+ self.fake_clk.pio = bus.master
+ self.fake_membnks.pio = bus.master
+ self.fake_l2_1.pio = bus.master
+ self.fake_l2_2.pio = bus.master
+ self.fake_l2_3.pio = bus.master
+ self.fake_l2_4.pio = bus.master
+ self.fake_l2esr_1.pio = bus.master
+ self.fake_l2esr_2.pio = bus.master
+ self.fake_l2esr_3.pio = bus.master
+ self.fake_l2esr_4.pio = bus.master
+ self.fake_ssi.pio = bus.master
+ self.fake_jbi.pio = bus.master
+ self.puart0.pio = bus.master
+ self.hvuart.pio = bus.master