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| author | Adrian Herrera <adrian.herrera@arm.com> | 2019-12-12 16:25:46 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2020-01-06 15:44:49 +0000 |
| commit | 6d37f2877ef27dcec1eb1d39e7f06b3e2386bcb8 (patch) | |
| tree | 6821eb4b45b8c204429a4acabb18d633244b86af /src | |
| parent | 44e3c95555b380f62c3fa4d878d78f26ad035475 (diff) | |
| download | gem5-6d37f2877ef27dcec1eb1d39e7f06b3e2386bcb8.tar.xz | |
dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour
Architecture states write accesses to GICR_ICFGR0 are WI. This patch
implements handling of this behaviour instead of crashing as an invalid
offset. This is required to support certain software behaviour.
Change-Id: I1f8c57838566c360d243a925306ec35c64a920b2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24063
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/dev/arm/gic_v3_redistributor.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc index 75fd9b326..f071c5bc7 100644 --- a/src/dev/arm/gic_v3_redistributor.cc +++ b/src/dev/arm/gic_v3_redistributor.cc @@ -579,6 +579,9 @@ Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size, break; + case GICR_ICFGR0: // SGI Configuration Register + // WI + return; case GICR_ICFGR1: { // PPI Configuration Register int first_intid = Gicv3::SGI_MAX; |