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authorNilay Vaish <nilay@cs.wisc.edu>2014-11-06 05:41:44 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-11-06 05:41:44 -0600
commit95a0b184314cf0171a20fb7e71c845891dc56496 (patch)
tree00590e68aa9d66c225a8f0d08f82eca2771e461d /src
parent8ccfd9defa930d5c2904134d7a7286682e721db9 (diff)
downloadgem5-95a0b184314cf0171a20fb7e71c845891dc56496.tar.xz
ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby.
Diffstat (limited to 'src')
-rw-r--r--src/mem/protocol/MESI_Two_Level-dma.sm5
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-dma.sm5
-rw-r--r--src/mem/protocol/MOESI_CMP_token-dma.sm5
-rw-r--r--src/mem/ruby/system/DMASequencer.cc23
-rw-r--r--src/mem/ruby/system/DMASequencer.hh5
-rw-r--r--src/mem/ruby/system/Sequencer.py5
6 files changed, 10 insertions, 38 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm
index e31832620..845d4df2f 100644
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm
@@ -49,11 +49,6 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- structure(DMASequencer, external="yes") {
- void ackCallback();
- void dataCallback(DataBlock);
- }
-
MessageBuffer mandatoryQueue, ordered="false";
State cur_state;
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index 767a51a1f..9bdd791e1 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -62,11 +62,6 @@ machine(DMA, "DMA Controller")
DataBlock DataBlk, desc="Data";
}
- structure(DMASequencer, external = "yes") {
- void ackCallback();
- void dataCallback(DataBlock);
- }
-
structure(TBETable, external = "yes") {
TBE lookup(Address);
void allocate(Address);
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index 72b0e52a5..1c28971a1 100644
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -51,11 +51,6 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- structure(DMASequencer, external="yes") {
- void ackCallback();
- void dataCallback(DataBlock);
- }
-
MessageBuffer mandatoryQueue, ordered="false";
State cur_state;
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 66b6e404a..eb4ce6123 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -40,9 +40,8 @@
DMASequencer::DMASequencer(const Params *p)
: MemObject(p), m_version(p->version), m_controller(NULL),
m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester),
- slave_port(csprintf("%s.slave", name()), this, access_phys_mem, 0),
- drainManager(NULL), system(p->system), retry(false),
- access_phys_mem(p->access_phys_mem)
+ slave_port(csprintf("%s.slave", name()), this, 0),
+ drainManager(NULL), system(p->system), retry(false)
{
assert(m_version != -1);
}
@@ -56,6 +55,8 @@ DMASequencer::init()
m_mandatory_q_ptr->setSender(this);
m_is_busy = false;
m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
+
+ slave_port.sendRangeChange();
}
BaseSlavePort &
@@ -72,9 +73,8 @@ DMASequencer::getSlavePort(const std::string &if_name, PortID idx)
}
DMASequencer::MemSlavePort::MemSlavePort(const std::string &_name,
- DMASequencer *_port, bool _access_phys_mem, PortID id)
- : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
- access_phys_mem(_access_phys_mem)
+ DMASequencer *_port, PortID id)
+ : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this)
{
DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name);
}
@@ -202,28 +202,21 @@ void
DMASequencer::MemSlavePort::hitCallback(PacketPtr pkt)
{
bool needsResponse = pkt->needsResponse();
- bool accessPhysMem = access_phys_mem;
-
assert(!pkt->isLLSC());
assert(!pkt->isFlush());
DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse);
- if (accessPhysMem) {
- DMASequencer *seq = static_cast<DMASequencer *>(&owner);
- seq->system->getPhysMem().access(pkt);
- } else if (needsResponse) {
- pkt->makeResponse();
- }
-
// turn packet around to go back to requester if response expected
if (needsResponse) {
+ pkt->makeResponse();
DPRINTF(RubyDma, "Sending packet back over port\n");
// send next cycle
schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
} else {
delete pkt;
}
+
DPRINTF(RubyDma, "Hit callback done!\n");
}
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index a24db2d34..be386f1a1 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -66,11 +66,10 @@ class DMASequencer : public MemObject
{
private:
SlavePacketQueue queue;
- bool access_phys_mem;
public:
MemSlavePort(const std::string &_name, DMASequencer *_port,
- bool _access_phys_mem, PortID id);
+ PortID id);
void hitCallback(PacketPtr pkt);
void evictionCallback(const Address& address);
@@ -140,8 +139,6 @@ class DMASequencer : public MemObject
System* system;
bool retry;
- bool access_phys_mem;
-
bool m_is_busy;
uint64_t m_data_block_mask;
DMARequest active_request;
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 8bad83db5..6f64207dc 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -73,12 +73,9 @@ class RubySequencer(RubyPort):
class DMASequencer(MemObject):
type = 'DMASequencer'
cxx_header = "mem/ruby/system/DMASequencer.hh"
- version = Param.Int(0, "")
+ version = Param.Int(0, "")
slave = SlavePort("Device slave port")
-
using_ruby_tester = Param.Bool(False, "")
- access_phys_mem = Param.Bool(True,
- "should the dma atomically update phys_mem")
ruby_system = Param.RubySystem(Parent.any, "")
system = Param.System(Parent.any, "system object")