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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-11 13:32:20 +0000 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-25 12:55:27 +0000 |
commit | 9b6f0a97680a825d7ebfe13878fe10490f97c0be (patch) | |
tree | 8d63af4aad07f78d3937c297300eee1e351c41b1 /src | |
parent | 96e72d6ecdf703f09d2788d02d5bedcf7b4b43f8 (diff) | |
download | gem5-9b6f0a97680a825d7ebfe13878fe10490f97c0be.tar.xz |
arch-arm: Remove floatReg operand type
Change-Id: I87553257ce9c42d0e2514d5a1f010bc6e2e7f21e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15604
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/arm/isa/operands.isa | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index dc54ec2d5..025f75755 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -129,9 +129,6 @@ let {{ def vectorRegElem(elem, ext = 'sf', zeroing = False): return (elem, ext, zeroing) - def floatReg(idx): - return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal) - def intReg(idx): return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, maybePCRead, maybePCWrite) |