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authorBrandon Potter <brandon.potter@amd.com>2015-07-10 16:05:23 -0500
committerBrandon Potter <brandon.potter@amd.com>2015-07-10 16:05:23 -0500
commit9eda4bdc5a947883a2d55ab860d37c5cd80c3370 (patch)
tree0dc23e2bdca0338129ba473e259f891a2edb15c1 /src
parenta74c446e7d034cebe01babb92f448a145b4ba77d (diff)
downloadgem5-9eda4bdc5a947883a2d55ab860d37c5cd80c3370.tar.xz
ruby: remove extra whitespace and correct misspelled words
Diffstat (limited to 'src')
-rw-r--r--src/mem/ruby/network/MessageBuffer.hh2
-rw-r--r--src/mem/ruby/network/Network.hh2
-rw-r--r--src/mem/ruby/network/garnet/BaseGarnetNetwork.hh8
-rw-r--r--src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh6
-rw-r--r--src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc10
-rw-r--r--src/mem/ruby/network/simple/SimpleNetwork.cc12
-rw-r--r--src/mem/ruby/structures/BankedArray.hh3
-rw-r--r--src/mem/ruby/system/DMASequencer.cc2
-rw-r--r--src/mem/ruby/system/RubyPort.cc4
-rw-r--r--src/mem/ruby/system/Sequencer.cc2
-rw-r--r--src/mem/ruby/system/System.cc10
-rw-r--r--src/mem/slicc/symbols/StateMachine.py6
-rw-r--r--src/mem/slicc/symbols/Type.py4
13 files changed, 36 insertions, 35 deletions
diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh
index b5d2b9eca..604d7bc7d 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -180,7 +180,7 @@ class MessageBuffer
Cycles m_time_last_time_size_checked;
unsigned int m_size_last_time_size_checked;
- // variables used so enqueues appear to happen imediately, while
+ // variables used so enqueues appear to happen immediately, while
// pop happen the next cycle
Cycles m_time_last_time_enqueue;
Tick m_time_last_time_pop;
diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh
index 6b6258b2b..24a487d25 100644
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -61,7 +61,7 @@ class Network : public ClockedObject
typedef RubyNetworkParams Params;
Network(const Params *p);
const Params * params() const
- { return dynamic_cast<const Params *>(_params);}
+ { return dynamic_cast<const Params *>(_params); }
virtual ~Network();
virtual void init();
diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh b/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
index cc1d4d929..a977f06e6 100644
--- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
+++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
@@ -41,16 +41,16 @@
#include "mem/ruby/network/fault_model/FaultModel.hh"
#include "params/BaseGarnetNetwork.hh"
-class BaseGarnetNetwork : public Network
+class BaseGarnetNetwork : public Network
{
public:
typedef BaseGarnetNetworkParams Params;
BaseGarnetNetwork(const Params *p);
void init();
- int getNiFlitSize() {return m_ni_flit_size; }
- int getVCsPerVnet() {return m_vcs_per_vnet; }
- bool isFaultModelEnabled() {return m_enable_fault_model;}
+ int getNiFlitSize() { return m_ni_flit_size; }
+ int getVCsPerVnet() { return m_vcs_per_vnet; }
+ bool isFaultModelEnabled() { return m_enable_fault_model; }
FaultModel* fault_model;
void increment_injected_flits(int vnet) { m_flits_injected[vnet]++; }
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
index 738a28cf7..efd70c3a0 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
@@ -54,8 +54,8 @@ class GarnetNetwork_d : public BaseGarnetNetwork
~GarnetNetwork_d();
void init();
- int getBuffersPerDataVC() {return m_buffers_per_data_vc; }
- int getBuffersPerCtrlVC() {return m_buffers_per_ctrl_vc; }
+ int getBuffersPerDataVC() { return m_buffers_per_data_vc; }
+ int getBuffersPerCtrlVC() { return m_buffers_per_ctrl_vc; }
void collateStats();
void regStats();
@@ -69,7 +69,7 @@ class GarnetNetwork_d : public BaseGarnetNetwork
}
// Methods used by Topology to setup the network
- void makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
+ void makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
LinkDirection direction,
const NetDest& routing_table_entry);
void makeInLink(NodeID src, SwitchID dest, BasicLink* link,
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
index 07d5412d0..8951f7513 100644
--- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
@@ -94,8 +94,8 @@ GarnetNetwork::~GarnetNetwork()
}
void
-GarnetNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link,
- LinkDirection direction,
+GarnetNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link,
+ LinkDirection direction,
const NetDest& routing_table_entry)
{
assert(src < m_nodes);
@@ -110,8 +110,8 @@ GarnetNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link,
}
void
-GarnetNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
- LinkDirection direction,
+GarnetNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
+ LinkDirection direction,
const NetDest& routing_table_entry)
{
assert(dest < m_nodes);
@@ -130,7 +130,7 @@ GarnetNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
void
GarnetNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
- LinkDirection direction,
+ LinkDirection direction,
const NetDest& routing_table_entry)
{
GarnetIntLink* garnet_link = safe_cast<GarnetIntLink*>(link);
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc
index 074052cb9..7426e9691 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -83,8 +83,8 @@ SimpleNetwork::~SimpleNetwork()
// From a switch to an endpoint node
void
-SimpleNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
- LinkDirection direction,
+SimpleNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
+ LinkDirection direction,
const NetDest& routing_table_entry)
{
assert(dest < m_nodes);
@@ -102,8 +102,8 @@ SimpleNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
// From an endpoint node to a switch
void
-SimpleNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link,
- LinkDirection direction,
+SimpleNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link,
+ LinkDirection direction,
const NetDest& routing_table_entry)
{
assert(src < m_nodes);
@@ -112,8 +112,8 @@ SimpleNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link,
// From a switch to a switch
void
-SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
- LinkDirection direction,
+SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
+ LinkDirection direction,
const NetDest& routing_table_entry)
{
// Create a set of new MessageBuffers
diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh
index 7cc6563d4..ed9269eaa 100644
--- a/src/mem/ruby/structures/BankedArray.hh
+++ b/src/mem/ruby/structures/BankedArray.hh
@@ -61,7 +61,8 @@ class BankedArray
unsigned int mapIndexToBank(int64 idx);
public:
- BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit);
+ BankedArray(unsigned int banks, Cycles accessLatency,
+ unsigned int startIndexBit);
// Note: We try the access based on the cache index, not the address
// This is so we don't get aliasing on blocks being replaced
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 05592b231..646601ad4 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -304,7 +304,7 @@ DMASequencer::issueNext()
assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr->enqueue(msg);
active_request.bytes_issued += msg->getLen();
- DPRINTF(RubyDma,
+ DPRINTF(RubyDma,
"DMA request bytes issued %d, bytes completed %d, total len %d\n",
active_request.bytes_issued, active_request.bytes_completed,
active_request.len);
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index d34cb3c2f..94f0c0966 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -363,7 +363,7 @@ RubyPort::ruby_hit_callback(PacketPtr pkt)
if (!retryList.empty()) {
//
// Record the current list of ports to retry on a temporary list before
- // calling sendRetry on those ports. sendRetry will cause an
+ // calling sendRetry on those ports. sendRetry will cause an
// immediate retry, which may result in the ports being put back on the
// list. Therefore we want to clear the retryList before calling
// sendRetry.
@@ -422,7 +422,7 @@ RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
{
bool needsResponse = pkt->needsResponse();
- // Unless specified at configuraiton, all responses except failed SC
+ // Unless specified at configuraiton, all responses except failed SC
// and Flush operations access M5 physical memory.
bool accessPhysMem = access_backing_store;
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 0a48817ca..a5e26b800 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -347,7 +347,7 @@ Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
} else {
//
// For successful SC requests, indicate the success to the cpu by
- // setting the extra data to one.
+ // setting the extra data to one.
//
request->pkt->req->setExtraData(1);
}
diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc
index 9d63643cc..2f1d9013c 100644
--- a/src/mem/ruby/system/System.cc
+++ b/src/mem/ruby/system/System.cc
@@ -86,16 +86,16 @@ RubySystem::RubySystem(const Params *p)
void
RubySystem::registerNetwork(Network* network_ptr)
{
- m_network = network_ptr;
+ m_network = network_ptr;
}
void
RubySystem::registerAbstractController(AbstractController* cntrl)
{
- m_abs_cntrl_vec.push_back(cntrl);
+ m_abs_cntrl_vec.push_back(cntrl);
- MachineID id = cntrl->getMachineID();
- g_abs_controls[id.getType()][id.getNum()] = cntrl;
+ MachineID id = cntrl->getMachineID();
+ g_abs_controls[id.getType()][id.getNum()] = cntrl;
}
RubySystem::~RubySystem()
@@ -189,7 +189,7 @@ RubySystem::serializeOld(CheckpointOut &cp)
// Restore curTick
setCurTick(curtick_original);
- // Aggergate the trace entries together into a single array
+ // Aggregate the trace entries together into a single array
uint8_t *raw_data = new uint8_t[4096];
uint64 cache_trace_size = m_cache_recorder->aggregateRecords(&raw_data,
4096);
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 8b7a63f6a..c5ad75145 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -225,7 +225,7 @@ class $py_ident(RubyController):
"in StateMachine.py", param.type_ast.type.c_ident)
code.dedent()
code.write(path, '%s.py' % py_ident)
-
+
def printControllerHH(self, path):
'''Output the method declarations for the class declaration'''
@@ -509,7 +509,7 @@ $c_ident::$c_ident(const Params *p)
if re.compile("sequencer").search(param.ident):
code('m_${{param.ident}}_ptr->setController(this);')
-
+
for var in self.objects:
if var.ident.find("mandatoryQueue") >= 0:
code('''
@@ -1501,7 +1501,7 @@ if (!checkResourceAvailable(%s_RequestType_%s, addr)) {
</TR>
''')
code('''
-<!- Column footer->
+<!- Column footer->
<TR>
<TH> </TH>
''')
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index e6e704000..fecc637d9 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -470,8 +470,8 @@ enum ${{self.c_ident}} {
# For each field
for i,(ident,enum) in enumerate(self.enums.iteritems()):
desc = enum.get("desc", "No description avaliable")
- if i == 0:
- init = ' = %s_FIRST' % self.c_ident
+ if i == 0:
+ init = ' = %s_FIRST' % self.c_ident
else:
init = ''
code('${{self.c_ident}}_${{enum.ident}}$init, /**< $desc */')