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| author | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2015-05-05 03:22:42 -0400 |
|---|---|---|
| committer | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2015-05-05 03:22:42 -0400 |
| commit | a3f23894ebf8dc237094ea47ef483484e8df412f (patch) | |
| tree | 2797128e93f459a18734b4f425309a99371ce99f /src | |
| parent | 80cd107e51ceb5aac262ec7dd82870e48d345b43 (diff) | |
| download | gem5-a3f23894ebf8dc237094ea47ef483484e8df412f.tar.xz | |
arm: enable DCZVA by default in SE mode
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 2ad256273..07d938f6a 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013 ARM Limited + * Copyright (c) 2010-2013, 2015 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -43,6 +43,7 @@ #include "arch/arm/miscregs.hh" #include "base/misc.hh" #include "cpu/thread_context.hh" +#include "sim/full_system.hh" namespace ArmISA { @@ -2138,7 +2139,9 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) if (el == EL0 && !sctlr.uma) return false; } - if (reg == MISCREG_DC_ZVA_Xt) { + if (FullSystem && reg == MISCREG_DC_ZVA_Xt) { + // In syscall-emulation mode, this test is skipped and DCZVA is always + // allowed at EL0 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); if (el == EL0 && !sctlr.dze) return false; |