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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
commita706b6259a3cab71700078c4e2b91860cc2219c0 (patch)
tree19191bbcb0f466e17b7cf56c0cb569689cb2647a /src
parent5060e572ca07b98f7d84679bac81c0151dee46b9 (diff)
downloadgem5-a706b6259a3cab71700078c4e2b91860cc2219c0.tar.xz
ruby: cache memory: drop {try,test}CacheAccess functions
Diffstat (limited to 'src')
-rw-r--r--src/mem/ruby/structures/CacheMemory.cc50
-rw-r--r--src/mem/ruby/structures/CacheMemory.hh9
2 files changed, 0 insertions, 59 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index 931f58a8e..ac6f823ce 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -158,56 +158,6 @@ CacheMemory::getAddressAtIdx(int idx) const
return entry->m_Address;
}
-bool
-CacheMemory::tryCacheAccess(Addr address, RubyRequestType type,
- DataBlock*& data_ptr)
-{
- assert(address == makeLineAddress(address));
- DPRINTF(RubyCache, "address: %s\n", address);
- int64_t cacheSet = addressToCacheSet(address);
- int loc = findTagInSet(cacheSet, address);
- if (loc != -1) {
- // Do we even have a tag match?
- AbstractCacheEntry* entry = m_cache[cacheSet][loc];
- m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
- data_ptr = &(entry->getDataBlk());
-
- if (entry->m_Permission == AccessPermission_Read_Write) {
- return true;
- }
- if ((entry->m_Permission == AccessPermission_Read_Only) &&
- (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) {
- return true;
- }
- // The line must not be accessible
- }
- data_ptr = NULL;
- return false;
-}
-
-bool
-CacheMemory::testCacheAccess(Addr address, RubyRequestType type,
- DataBlock*& data_ptr)
-{
- assert(address == makeLineAddress(address));
- DPRINTF(RubyCache, "address: %s\n", address);
- int64_t cacheSet = addressToCacheSet(address);
- int loc = findTagInSet(cacheSet, address);
-
- if (loc != -1) {
- // Do we even have a tag match?
- AbstractCacheEntry* entry = m_cache[cacheSet][loc];
- m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
- data_ptr = &(entry->getDataBlk());
-
- return m_cache[cacheSet][loc]->m_Permission !=
- AccessPermission_NotPresent;
- }
-
- data_ptr = NULL;
- return false;
-}
-
// tests to see if an address is present in the cache
bool
CacheMemory::isTagPresent(Addr address) const
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 7ce674e61..94174b286 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -56,15 +56,6 @@ class CacheMemory : public SimObject
void init();
- // Public Methods
- // perform a cache access and see if we hit or not. Return true on a hit.
- bool tryCacheAccess(Addr address, RubyRequestType type,
- DataBlock*& data_ptr);
-
- // similar to above, but doesn't require full access check
- bool testCacheAccess(Addr address, RubyRequestType type,
- DataBlock*& data_ptr);
-
// tests to see if an address is present in the cache
bool isTagPresent(Addr address) const;